Datasheet

APPLICATION INFORMATION
BASIC CIRCUIT CONFIGURATION
AGND
GPO2
GPO3
OVR
1
3
4
6
PGA2505
ToRelayDrivers
and Switches
DGND
7
To/From
MPU,MCU,
DSP,orLogic
SDI
CS
SCLK
SDO
11
13
12
VD-
VA-
15
14
V +
IN
V -
IN
0W
24
23
8
9
10
C
S21
C
S22
19
18
10W
0.1 Fm
VA-
0.1 Fm
+
4.7 Fm
+
4.7 Fm
V +
OUT
17
0.1 Fm
1 Fm
C
S11
C
S12
21
20
1 Fm
V -
OUT
VA-
VA+
VA-
+
4.7 Fm
VA+
V IN
COM
22
16
0.1 Fm
+
4.7 Fm
0.1 Fm
GPO1
2
GPO4
5
PGA2505
SBOS396B – MARCH 2009 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com
with analog and digital pins separated basically down
the center of the package. (Note that AGND is on the
This section provides practical information for
opposite side.) However, there must be a low
designing the PGA2505 into end applications.
impedance connection between the analog and digital
grounds at a common return point.
The dc common-mode input, V
COM
IN (pin 22), can be
A typical application configuration, without the input
connected to analog ground or a dc voltage (such as
and output circuitry, is shown in Figure 13 .
the reference or common voltage output of an audio
Power-supply bypass and dc servo capacitors are
ADC). When biasing this input to a dc voltage, keep
shown with recommended values. All capacitors
in mind that both the analog output and input pins will
should be placed as close as possible to the
be level-shifted by the value of the bias voltage.
PGA2505 package to limit inductive noise coupling.
Surface-mount capacitors are recommended (X7R
ceramic for the 0.1 µ F and 1 µ F capacitors, and low
ESR tantalum for the 4.7 µ F capacitors).
The PGA2505 can be placed on a split ground plane,
Figure 13. Basic Circuit Configuration for the PGA2505
12 Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): PGA2505