Datasheet

DAISY-CHAINING MULTIPLE PGA2505
CS
SCLK
SDI
SDO
V
OUT
+
V
OUT
-
V
IN
+
V
IN
-
PGA2505
#1
CS
SCLK
SDI
SDO
V
OUT
+
V
OUT
-
V
IN
+
V
IN
-
PGA2505
#2
CS
SCLK
SDI
SDO
V
OUT
+
V
OUT
-
V
IN
+
V
IN
-
PGA2505
#N
CS
DATACLK
DOUT
DIN
Microprocessor
orDSP
SCLK
CS
SDI
DC G0
DC G0
DC
Device#1
Device#2
Device#N
G0
PGA2505
www.ti.com ......................................................................................................................................................... SBOS396B – MARCH 2009 – REVISED JUNE 2009
PREAMPLIFIERS
Because the serial port interface may be viewed as a To program all of the devices, simply force CS low for
serial in, serial out shift register, multiple PGA2505 16 x N serial clock periods and clock in 16 x N bits of
preamplifiers may be connected in a cascaded or control data. The CS input is then forced high to latch
daisy-chained fashion, as shown in Figure 11 . The in the new settings.
daisy-chained PGA2505 devices behave as a 16 x
A timing diagram for the daisy-chain application is
N-bit shift register, where N is the number of
shown in Figure 12 .
cascaded PGA2505 devices.
Figure 11. Daisy-Chain Configuration for Multiple PGA2505 Preamplifiers
Figure 12. Serial Port Operation for Daisy-Chain Operation
Copyright © 2009, Texas Instruments Incorporated 11
Product Folder Link(s): PGA2505