Datasheet

SERIAL PORT OPERATION
SCLK
DC CM ZC OR D4 D3 D2 D1 0 0 G5 G4 G3 G2 G1 G0
DataIgnored
DataIgnored
DC CM ZC OR D4 D3 D2 D1 0 0 G5 G4 G3 G2 G1 G0
HighImpedance
HighImpedance
CS
SDI
SDO
DCServoEnable
(ActiveLow)
CMServoEnable
(ActiveHigh)
Over-RangeIndicatorBit
(0=5.1V ,1=4.0V )
RMS RMS
DataforGPO4
DataforGPO2
DataforGPO1
PreamplifierGain
whereN=G[5:0]
DEC
ForN=0
Gain=0dB
ForN=1to17
Gain(dB)=6+3N
ForN=18to31
Gain=60dB
DataforGPO3
ZeroCrossingDetect
(ActiveHigh)
PGA2505
SBOS396B – MARCH 2009 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com
The SCLK input is used to clock serial data into the
SDI pin and out of the SDO pin. The SDI pin
The serial port interface for the PGA2505 is
functions as the serial data input, and is used to write
comprised of four wires: CS (pin 9), SCLK (pin 10),
the serial port register. The SDO pin is the shift
SDI (pin 8), and SDO (pin 11). Figure 10 illustrates
register serial output, and is used for either register
the serial port protocol.
read-back or for daisy-chaining multiple PGA2505
devices. Data on SDI are sampled on the rising edge
The CS input functions as the chip select and word
of SCLK, while data are clocked out of SDO on the
latch clock for the serial port. The CS input must be
falling edge of SCLK.
low in order to clock data into and out of the serial
port. The control word is latched on a low-to-high
transition of the CS input.
The serial port ignores the SCLK and SDI inputs
when CS is high, and the SDO output is set to a high
impedance state while CS is high.
Figure 10. Serial Port Protocol
10 Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): PGA2505