Datasheet

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SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
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9
SERIAL PORT OPERATION
The serial port interface for the PGA2500 is comprised of
four wires: CS
(pin 11), SCLK (pin 12), SDI (pin 10), and
SDO (pin 13). Figure 2 illustrates the serial port protocol,
while Figure 3 and the Electrical Characteristics table
provide detailed timing parameters for the port.
The CS
input functions as the chip select and word latch
clock for the serial port. The CS
input must be low in order
to clock data into and out of the serial port. The control
word is latched on a low-to-high transition of the CS input.
The serial port ignores the SCLK and SDI inputs when CS
is high, and the SDO output is set to a high impedance
state while CS
is high.
The SCLK input is used to clock serial data into the SDI pin
and out of the SDO pin. The SDI pin functions as the serial
data input, and is used to write the serial port register. The
SDO pin is the shift register serial output, and is used for
either register read-back or for daisy-chaining multiple
PGA2500 devices. Data on SDI is sampled on the rising
edge of SCLK, while data is clocked out of SDO on the
falling edge of SCLK.
When the 0dB input (pin 8) is forced high, the gain set by
the serial port register will be overridden. The serial port
register may be updated while the 0dB input is forced high,
but the programmed gain will not take effect until the 0dB
input is forced low.
SCLK
DC CM 0 OL D4 D3 D2 D1 0 0 G5 G4 G3 G2 G1 G0
Data Ignored
Data Ignored
DC CM 0 OL D4 D3 D2 D1 0 0 G5 G4 G3 G2 G1 G0
High Impedance
High Impedance
CS
SDI
SDO
DC Servo Enable
(Active Low)
CM Servo Enable
(Active High)
Overload Indicator Bit
(0 = 5.1V
RMS
,1=4.0V
RMS
)
Data for GPO4
Data for GPO3
Data for GPO2
Data for GPO1
Preamplifier Gain
where N = G[5:0]
DEC
For N = 0
Gain = 0dB
For N = 1 to 56
Gain (dB) = 9 + N
For N = 57 to 63
Gain (dB) = 65
Figure 2. Serial Port Protocol
SCLK
SDI
SDO
t
CSO
MSB
MSB
t
CFDO
t
CSCR
t
SDS
t
SDH
t
CFCS
t
CSZ
CS
Figure 3. Serial Port Timing Requirements