Datasheet

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SBOS312B − JULY 2004 − REVISED DECEMBER 2004
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4
PIN CONFIGURATION
Top View
ZCEN
CS
SDI
V
D
+
DGND
SCLK
SDO
MUTE
V
IN
L
AGNDL
V
OUT
L
V
A
−
V
A
+
V
OUT
R
AGNDR
V
IN
R
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PGA2320
PIN ASSIGNMENTS
PIN NAME FUNCTION
1 ZCEN Zero Crossing Enable Input (Active High)
2 CS Chip-Select Input (Active Low)
3 SDI Serial Data input
4 V
D
+ Digital Power Supply, +5V
5 DGND Digital Ground
6 SCLK Serial Clock Input
7 SDO Serial Data Output
8 MUTE Mute Control Input (Active Low)
9 V
IN
R Analog Input, Right Channel
10 AGNDR Analog Ground, Right Channel
11 V
OUT
R Analog Output, Right Channel
12 V
A
+ Analog Power Supply, +15V
13 V
A
− Analog Power Supply, −15V
14 V
OUT
L Analog Output, Left Channel
15 AGNDL Analog Ground, Left Channel
16 V
IN
L Analog Input, Left Channel