Datasheet

14PGA204/205
®
GAIN
PGA205
PGA205
1
2
4
8
16
32
64
A
3
0
0
1
1
1
1
1
A
2
0
1
0
1
1
1
1
A
1
0
0
0
0
0
1
1
A
0
0
0
0
0
1
0
1
V
IN
+
V
IN
–
V
O
A
O
A
1
A
O
A
1
PGA204
PGA205
V
IN
–
V
IN
+
OPA177
20kΩ
Ref
V
O
220Ω
20kΩ
V
O2
V
O1
A
0
A
1
A
1
A
0
A
1
A
2
A
3
12
11
10
25kΩ25kΩ
25kΩ25kΩ
13
7
5
14
16
4
V+
PGA204
PGA205
Ref
V
O
Feedback
Digitally Selected
Feedback Network
1
V
O1
15
A
1
A
0
6 9 8
V
O2
V–V
OS
Adj
10
11
12
13
7
6
5
4
8
9
V
IN
–
V
IN
+
Data Out
74HC574
Data In
315 1 16
To Address
Decoding Logic
Data Bus
A
1
A
0
HI-509
–15V
+15V
14 2
Over-Voltage
Protection
Over-Voltage
Protection
CK
FIGURE 7. Multiplexed-Input Programmable Gain IA.
FIGURE 8. Shield Drive Circuit.
FIGURE 9. Binary Gain Steps, G=1 to G=64. FIGURE 10. AC-Coupled PGIA.
PGA204
PGA205
V
O
C
1

0.1µF
OPA602
Ref
R
1

1MΩ
f
–3dB
=
1
2πR
1
C
1
= 1.59Hz
V
IN
+
–
A
1
A
0