Datasheet

SPI TIMING: V
S
= AV
DD
= DV
DD
= +2.2V to +5V
PGA112 , , PGA113
PGA116 , PGA117
SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com
Boldface limits apply over the specified temperature range, T
A
= – 40 ° C to +125 ° C.
At T
A
= +25 ° C, R
L
= 10k Ω //C
L
= 100pF connected to DV
DD
/2, and V
REF
= GND, unless otherwise noted.
PGA112, PGA113,
PGA116, PGA117
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input Capacitance (SCLK, CS, and DIO pins) 1 pF
Input Rise/Fall Time
(1)
t
RFI
2 µ s
( CS, SCLK, and DIO pins)
Output Rise/Fall Time (DIO pin)
(1)
t
RFO
C
LOAD
= 60pF 10 ns
CS High Time ( CS pin)
(1)
t
CSH
40 ns
SCLK Edge to CS Fall Setup Time
(1)
t
CSO
10 ns
CS Fall to First SCLK Edge Setup Time t
CSSC
10 ns
SCLK Frequency
(2)
f
SCLK
10 MHz
SCLK High Time
(3)
t
HI
40 ns
SCLK Low Time
(3)
t
LO
40 ns
SCLK Last Edge to CS Rise Setup Time
(1)
t
SCCS
10 ns
CS Rise to SCLK Edge Setup Time
(1)
t
CS1
10 ns
DIN Setup Time t
SU
10 ns
DIN Hold Time t
HD
10 ns
SCLK to DOUT Valid Propagation Delay
(1)
t
DO
25 ns
CS Rise to DOUT Forced to Hi-Z
(1)
t
SOZ
20 ns
(1) Ensured by design; not production tested.
(2) When using devices in daisy-chain mode, the maximum clock frequency for SCLK is limited by SCLK rise/fall time, DIN setup time, and
DOUT propagation delay. See Figure 63 . Based on this limitation, the maximum SCLK frequency for daisy-chain mode is 9.09MHz.
(3) t
HI
and t
LO
must not be less than 1/SCLK (max).
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Product Folder Link(s): PGA112 PGA113 PGA116 PGA117