Datasheet

POWER SUPPLIES
SHUTDOWN AND POWER-ON-RESET (POR)
10kW
ADC
G=1
R
F
R
I
Output
Stage
SPI
Interface
SCLK
DIO
CS
7
V
OUT
5
DV
DD
10
AV
DD
1
GND
6
V
REF
4
3
8
9
MSP430
Microcontroller
+3V
+5V
V
REF
PGA112
PGA113
(MSOP-10)
V
CAL
/CH0
2
CH1
CAL3
CAL4
CAL1
CAL2
0.1V
CAL
0.9V
CAL
10kW
80kW
MUX
CAL2/3
PGA112 , , PGA113
PGA116 , PGA117
SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com
At initial power-on, the state of the PGA is G = 1 and
Channel 0 active. CAUTION: For most applications,
Figure 80 shows a typical mixed-supply voltage
set AV
DD
≥ DV
DD
to prevent V
OUT
from driving
system where the analog supply, AV
DD
, is +5V and
current into AV
DD
and raising the voltage level of
the digital supply voltage, DV
DD
, is +3V. The analog
AV
DD
.
output stage of the PGA and the SPI interface digital
circuitry are both powered from DV
DD
. When
considering the power required for DV
DD
, use the
Electrical Characteristics table and add any load
The PGA112/PGA113 have a software shutdown
current anticipated on V
OUT
; this load current must be
mode, and the PGA116/PGA117 offer both a
provided by DV
DD
. This split-supply architecture
hardware and software shutdown mode. When the
ensures compatible logic levels with the
PGA is shut down, it goes into a low-power standby
microcontroller. It also ensures that the PGA output
mode. The Electrical Characteristics table details the
cannot run the input for the onboard ADC into an
current draw in shutdown mode with and without the
overvoltage condition; this condition could cause
SPI interface being clocked. In shutdown mode, R
F
device latch-up and system lock-up, and require
and R
I
remain connected between V
OUT
and V
REF
.
power-supply sequencing. Each supply pin should be
When DV
DD
is less than 1.6V, the digital interface is
individually bypassed with a 0.1 µ F ceramic capacitor
disabled and the channel and gain selections are
directly at the device to ground. If there is only one
held to the respective POR states of Gain = 1 and
power supply in the system, AV
DD
and DV
DD
can both
Channel = V
CAL
/CH0. When DV
DD
is above 1.8V, the
be connected to the same supply; however, it is
digital interface is enabled and the POR gain and
recommended to use individual bypass capacitors
channel states remain unchanged until a valid SPI
directly at each respective supply pin to a single point
communication is received.
ground. V
OUT
is diode-clamped to AV
DD
(as shown in
Figure 80 ); therefore, set DV
DD
less than or equal to
AV
DD
+ 0.3V. DV
DD
and AV
DD
must be within the
operating voltage range of +2.2V to +5.5V.
Figure 80. Split Power-Supply Architecture: AV
DD
≠ DV
DD
40 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): PGA112 PGA113 PGA116 PGA117