Datasheet

APPLICATIONS: DRIVING/INTERFACING TO
10kW
CDACSAR
ADC
G=1
R
F
R
I
Output
Stage
SPI
Interface
SCLK
DIO
CS
7
V
OUT
5
DV
DD
10
AV
DD
1
GND
6
V
REF
4
3
8
9
+3V
+5V
V
REF
PGA112
PGA113
(MSOP-10)
V /CH0
CAL
2
CH1
CAL3
CAL4
CAL1
CAL2
0.1V
CAL
0.9V
CAL
10kW
80kW
MUX
CAL2/3
R
100W
FILT
C
FILT
(1nF)
C
SH
40pF
12-BitSettling 500kHz
16-BitSettling 300kHz
®
®
C
0.1 F
BYPASS
m
C
0.1 F
BYPASS
m
C
0.1 F
BYPASS
m
PGA112 , , PGA113
PGA116 , PGA117
www.ti.com ............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008
2. Signal trace routing. Keep V
OUT
and other low Bypass capacitors greater than 100pF are
impedance traces away from MUX channel inputs recommended. Lower impedances and a bypass
that are high impedance. Poor signal routing can capacitor placed directly at the input MUX
cause positive feedback, unwanted oscillations, channels keep crosstalk between channels to a
or excessive overshoot and ringing on minimum as a result of parasitic capacitive
step-changing signals. If the input signals are coupling from adjacent PCB traces and pin-to-pin
particularly noisy, separate MUX input channels capacitance.
with guard traces on either side of the signal
traces. Connect the guard traces to ground near
the PGA and at the signal entry point into the
ADCS
PCB. On multilayer PCBs, ensure that there are
CDAC SAR ADCs contain an input sampling
no parallel traces near MUX input traces on
capacitor, C
SH
, to sample the input signal during a
adjacent layers; capacitive coupling from other
sample period as shown in Figure 79 . After the
layers can be a problem. Use ground planes to
sample period, C
SH
is removed from the input signal.
isolate MUX input signal traces from signal traces
Subsequent comparisons of the charge stored on C
SH
on other layers.
are performed during the ADC conversion process.
Additionally, group and route the digital signals
To achieve optimal op amp stability, input signal
into the PGA as far away as possible from the
settling, and the demands for charge from the input
analog MUX input signals. Most digital signals
signal conditioning circuitry, most ADC applications
are fast rise/fall time signals with low-impedance
are optimized by the use of a resistor (R
FILT
) and
drive capability that can easily couple into the
capacitor (C
FILT
) filter placed between the op amp
high-impedance inputs of the input MUX
output and ADC input. For the PGA112/PGA113, or
channels. This coupling can create unwanted
the PGA116/PGA117, setting C
FILT
= 1nF and R
FILT
=
noise that gains up to V
OUT
.
100 Ω yields optimum system performance for
sampling converters operating at speeds up to
3. Input MUX channels and source impedance.
500kHz, depending upon the application settling time
Input MUX channels are high-impedance; when
and accuracy requirements.
combined with high gain, the channels can pick
up unwanted noise. Keep the input signal
sources low-impedance ( < 10k Ω ). Also, consider
bypassing input MUX channels with a ceramic
bypass capacitor directly at the MUX input pin.
Figure 79. Driving/Interfacing to ADCs
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 39
Product Folder Link(s): PGA112 PGA113 PGA116 PGA117