Datasheet

10kW
ADC
G=1
R
F
R
I
Output
Stage
SPI
Interface
SCLK
DIO
CS
V
OUT
DV
DD
AV
DD
GND V
REF
MSP430
Microcontroller
+3V
+3V
V
REF
PGA112
PGA113
V /CH0
CAL
CH1
CAL3
CAL4
CAL1
CAL2
0.1V
CAL
0.9V
CAL
10kW
80kW
MUX
CAL2/3
ADCRef
OPA364
R
10kW
F
C
2.7nF
F
+3V
C
L2
0.1 Fm
0.1 Fm
R
Y
100kW
R
X
100kW
+3V
(1.5V)
C
0.1 F
BYPASS
m
C
0.1 F
BYPASS
m
C
0.1 F
BYPASS
m
C
0.1 F
BYPASS
m
PGA112 , , PGA113
PGA116 , PGA117
www.ti.com ............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008
Figure 74. Using CAL Channels with V
REF
= AV
DD
/2
Table 10. Using the MUX CAL Channels with V
REF
= AV
DD
/2
(AV
DD
= 3V, DV
DD
= 3V, ADC Ref = 3V, and V
REF
= 1.5V)
MUX GAIN OP AMP OP AMP
FUNCTION SELECT SELECT MUX INPUT (+In) (V
OUT
) DESCRIPTION
Minimum signal level that the MUX,
Minimum Signal CAL1 1 GND GND 50mV op amp, and ADC can read. Op amp
V
OUT
is limited by negative saturation.
0.9 × 90% ADC Ref for system full-scale or
Gain Calibration CAL2 1 2.7V 2.7V
(V
CAL
/CH0) gain calibration of the ADC.
Maximum signal level that the MUX,
0.9 ×
Maximum Signal CAL2 4 or 5 2.25V 2.95V op amp, and ADC can read. Op amp
(V
CAL
/CH0)
V
OUT
is limited by positive saturation.
0.1 × 10% ADC Ref for system offset
Offset Calibration CAL3 1 0.3V 0.3V
(V
CAL
/CH0) calibration of the ADC.
V
REF
Check CAL4 1 V
REF
1.5V 1.5V Midsupply voltage used as V
REF
.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 33
Product Folder Link(s): PGA112 PGA113 PGA116 PGA117