Datasheet

SCLK
DOUT1
DIN2
t
RFI
t
SU
t
MIN
=55ns
SCLK
MAX
=9.09MHz
t
MIN
=55ns
t
DO
t
RFI
10ns
10ns
25ns
10ns
PGA112 , , PGA113
PGA116 , PGA117
SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com
The maximum SCLK frequency that can be used in
daisy-chain operation is directly related to SCLK
rise/fall times, DIN setup time, and DOUT
propagation delay. Any number of two or more
devices have the same limitations because it is the
timing considerations between adjacent devices that
limit the clock speed.
Figure 63 analyzes the maximum SCLK frequency for
daisy-chain mode based on the circuit of Figure 61 . A
clock rise and fall time of 10ns is assumed to allow
for extra bus capacitance that could occur as a result
of multiple devices in the daisy-chain.
Figure 63. Daisy-Chain Maximum SCLK
Frequency
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Product Folder Link(s): PGA112 PGA113 PGA116 PGA117