Datasheet

PCM9211
www.ti.com SBAS495 –JUNE 2010
Register 6Bh, Main Output Port (SCKO/BCK/LRCK/DOUT) Source Setting
(Address: 6Bh, Write and Read)
DATA B7 B6 B5 B4 B3 B2 B1 B0
Reg Name RSV MOSSRC2 MOSSRC1 MOSSRC0 RSV MOPSRC2 MOPSRC1 MOPSRC0
Default Value 0 0 0 0 0 0 0 0
Memo
MOSSRC[2:0]: Main Output Port, SCK Source Control
000: DIR/ADC Automatic (DIR lock:DIR, DIR unlock:ADC) (default)
001: DIR
010: ADC
011: AUXIN0
100: AUXIN1
101: AUXIN2
110: Reserved
111: Reserved
MOPSRC[2:0]: Main Output Port, BCK/LRCK/DATA Source Control
000: DIR/ADC Automatic (DIR lock:DIR, DIR unlock:ADC) (default)
001: DIR
010: ADC
011: AUXIN0
100: AUXIN1
101: AUXIN2
110: Reserved
111: Reserved
This source control register is divided into two parts (MOSSRC and MOPSRC). This architecture allows some
additional functionality such as jitter cleaning. To clean the clock jitter of the HDMI receiver output, the HDMI
receiver S/PDIF output is connected with the PCM9211 S/PDIF input, and the HDMI receiver I
2
S outputs
(BCK/LRCK/DATA) are connected with the PCM9211 PCM input port.
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