Datasheet

PCM9211

SBAS495 –JUNE 2010

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(Address: 42h, Write and Read)

DATA B7 B6 B5 B4 B3 B2 B1 B0

Reg Name RSV RSV ADCKOUT ADDTRX7 ADFSLMT ADCLK2 ADCLK1 ADCLK0

Default Value 0 0 0 0 0 0 1 0

Memo

ADCKOUT: ADC Clock (SCK, BCK, LRCK) Output Select at ADC Power-Down

0: Output enable even at ADDIS = 1 (default)

1: Output disable at ADDIS = 0

ADDTRX7: ADC Output Data Select to Main Port, DOUT Pin

0: DOUT = ADC DOUT (default)

1: DOUT = RXIN7 (ADIN0)

This register can select an external ADC data from RXIN7 (ADIN0) to Main Port DOUT pin when

an external ADC is used.

ADFSLMT: ADC Sampling Frequency Limiter for DIR Clock Source

0: Disable (default)

1: Enable

When ADFSLMT = 1, ADCLK[2:0] = 001(ADC clock is DIR output clock) and DIR locks at

frequency from 14 kHz to 111 kHz, the ADC is forced into power down.

ADCLK[2:0]: ADC Clock Source (SCK/BCK/LRCK) Select

000: AUTO (DIR or XTI)

001: DIR

010: XTI (default)

011: AUXIN0

100: AUXIN1

100: AUXIN2

110: Reserved

111: Reserved

The ADC clock source must be normally set to XTI source with fixed frequency (the clocks at the XTI source

select are generated by the SCK/BCK/LRCK dividers). Its frequency is set by the register of XSCK[1:0],

XBCK[1:0], and XLRCK[1:0].).

Product Folder Link(s): PCM9211