Datasheet

PCM9211
SBAS495 –JUNE 2010 www.ti.com
Register 33h, XTI Source, Secondary Bit/LR Clock (SBCK/SLRCK) Frequency Setting
(Address: 33h, Write and Read)
DATA B7 B6 B5 B4 B3 B2 B1 B0
Reg Name RSV XSBCK2 XSBCK1 XSBCK0 RSV XSLRCK2 XSLRCK1 XSLRCK0
Default Value 0 0 1 0 0 0 1 0
Memo
XSBCK[2:0]: XTI Clock Source, Secondary BCK (SBCK) Frequency Setting
000: XTI/2 (12.288 MHz)
001: XTI/4 (6.144 MHz)
010: XTI/8 (3.072 MHz) (default)
011: XTI/16 (1.536 MHz)
100: XTI/32 (0.768 MHz)
101: Reserved
110: Reserved
111: Reserved
XSLRCK[2:0]: XTI Clock Source, Secondary LRCK (SLRCK) Frequency Setting
000: XTI/128 (192 kHz)
001: XTI/256 (96 kHz)
010: XTI/512 (48 kHz) (default)
011: XTI/1024 (24 kHz)
100: XTI/2048 (12 kHz)
101: Reserved
110: Reserved
111: Reserved
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