Datasheet

PCM9211
www.ti.com SBAS495 –JUNE 2010
Register 32h, DIR Source, Secondary Bit/LR Clock (SBCK/SLRCK) Frequency Setting
(Address: 32h, Write and Read)
DATA B7 B6 B5 B4 B3 B2 B1 B0
Reg Name RSV PSBCK2 PSBCK1 PSBCK0 RSV PSLRCK2 PSLRCK1 PSLRCK0
Default Value 0 0 1 0 0 0 1 0
Memo
PSBCK[2:0]: DIR Clock Source, Secondary BCK (SBCK) Frequency Setting
000: 16f
S
(BCK/4)
001: 32f
S
(BCK/2)
010: 64f
S
(1x BCK) (default)
011: 128f
S
(2x BCK)
100: 256f
S
(4x BCK)
101: Reserved
110: Reserved
111: Reserved
PSLRCK[2:0]: DIR Clock Source, Secondary LRCK (SLRCK) Frequency Setting
000: f
S
/4 (LRCK/4)
001: f
S
/2 (LRCK/2)
010: f
S
(1x LRCK) (default)
011: 2f
S
(2x LRCK)
100: 4f
S
(4x LRCK)
101: Reserved
110: Reserved
111: Reserved
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