Datasheet

t
M S S
LSB (D0)
MDI
MC
MS
t
MDH
t
MDS
t
MS H
t
MCH
t
MCL
t
MCY
1.4V
1.4V
1.4V
MDO
0.5*V
DD
t
MD D
t
MHH
t
MDR
LSB (D0 )MSB(D7)
MSB(R/W)
Hi -Z Hi -Z
t
M DD
ADR0
PCM9211
SBAS495 –JUNE 2010 www.ti.com
Timing Requirements
Figure 39 shows a detailed timing diagram for the four-wire serial control interface. These timing parameters are
critical for proper control port operation.
SYMBOL DESCRIPTION MIN MAX UNITS
t
MCY
MC Pulse cycle time 100 ns
t
MCL
MC Low level time 40 ns
t
MCH
MC High level time 40 ns
t
MHH
MS High level time t
MCY
ns
t
MSS
MS Falling edge to MC rising edge 30 ns
t
MSH
MS Rising edge from MC rising edge for LSB 15 ns
t
MDH
MDI Hold time 15 ns
t
MDS
MDI Set-up time 15 ns
t
MDD
MDO Enable or delay time from MC falling edge 0 30 ns
t
MDR
MDO Disable time from MS rising edge 0 30 ns
Figure 39. Control Interface Timing Requirements
Two-Wire (I
2
C) Serial Control
The PCM9211 also supports the I
2
C serial bus and data transmission protocol. It can be configured for fast mode
as a slave device. This protocol is explained fully in the I
2
C specification 2.1.
Slave Address
MSB LSB
1 0 0 0 0 ADR1 ADR0 R/W
The PCM9211 has seven bits for its own slave address. The first five bits (MSB) of the slave address are
factory-preset to '10000'. The next two bits of the address byte are selectable bits that can be set by MDO/ADR0
and MS/ADR1. A maximum of four PCM9211s can be connected on the same bus at one time. Each PCM9211
responds when it receives its own slave address.
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