Datasheet

Clock/ Data
Recovery
MPIO_A
SELECTOR
MPIO_C
SELECTOR
MPIO _B
SELECTOR
MPIO_B0
MPIO_B1
MPIO_B2
MPIO_B3
ADC
Com. Supply
MPO0/1
SELECTOR
MPO 0
MPO 1
MAIN
OUTPUT
SCKO (DSCKO)
BCK (DBCKO )
LRCK (DSDRO )
DOUT (DSDLO)
PORT
RXIN8
RXIN9
RXIN10
RXIN11
DITOUT
AUTO
DIR
ADC
AUXIN0
AUXIN1
AUXIN2
AUTO
DIR
ADC
AUXIN0
AUXIN1
AUXIN2
AUTO
DIR
ADC
AUXIN0
AUXIN1
DIT
Lock:DIR
Unlock:ADC
AUXIN 2
AUXOUT
DITOUT
RECOUT0
RECOUT1
AUXIN 0
AUXIN1
ADCStandalone
ADCMode
Control
FILT
PLL
DIR
LockDetection
ADC
RECOUT0
RECOUT1
DOUT
RXIN7
SCKOfromDIR
BCKfrom AUXIN 1
LRCKfrom AUXIN 1
RXIN 0
RXIN 1
RXIN 2
RXIN 4/ASCKI0
RXIN 3
RXIN 5/ABCKI0
RXIN 6/ALRCKI 0
RXIN 7/ADIN0 RXIN7
RXIN6
RXIN5
RXIN4
RXIN3
RXIN2
RXIN1
RXIN0
MPIO_A0
MPIO_A1
MPIO_A2
MPIO_A3
VINL
VINR
VCOM
MPIO _C0(DSCKI)
MPIO _C1(DBCKI)
MPIO _C2(DSDRI )
MPIO _C3(DSDLI )
PCM9211
www.ti.com SBAS495 –JUNE 2010
Figure 35 shows a block diagram of DSD Input Mode (this illustration includes an example of DSD input =
MPIO_Cx pins).
Note: Blue lines are through-paths for DBCKI, DSDRI, and DSDLI. Red lines are DSCKO generation paths.
Figure 35. DSD Input Mode Block Diagram
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