Datasheet

PCM9211
SBAS495 –JUNE 2010 www.ti.com
MPIO Description
Description for Signal Name Assigned to MPIO
Table 17 through Table 25 list the details of where each of the internal PCM9211 signals can be routed to. For
instance, DIR LOCK can be output to any of the MPIO and MPO pins, while SBCK (Secondary Clock Output)
can only be brought out through MPIO_A0.
Table 17. DIR Flags Output
SIGNAL NAME MPIO GROUP / PIN DESCRIPTION
CLKST All MPIOs, MPO0/1 Clock transient status signal output
INT0 All MPIOs, MPO0/1 Interrupt system 0, Interrupt event detection output
INT1 All MPIOs, MPO0/1 Interrupt system 1, Interrupt event detection output
EMPH All MPIOs, MPO0/1 Channel status, emphasis detection output
BPSYNC All MPIOs, MPO0/1 Burst preamble sync signal output
DTSCD All MPIOs, MPO0/1 DTS-CD/LD detection output
PARITY All MPIOs, MPO0/1 Biphase parity error detection output
LOCK All MPIOs, MPO0/1 PLL lock detection output
Table 18. DIR B Frame, Channel Status, User Data, Validity Flag Output
SIGNAL NAME MPIO GROUP / PIN DESCRIPTION
BFRAME All MPIOs, MPO0/1 B frame output
COUT All MPIOs Channel status data
UOUT All MPIOs User data
VOUT All MPIOs Validity flag
Table 19. DIR Calculated Sampling Frequency Output
SIGNAL NAME MPIO GROUP / PIN DESCRIPTION
SFSOUT0 All MPIOs Calculated f
S
, decoded output, bit0
SFSOUT1 All MPIOs Calculated f
S
, decoded output, bit1
SFSOUT2 All MPIOs Calculated f
S
, decoded output, bit2
SFSOUT3 All MPIOs Calculated f
S
, decoded output, bit3
Table 20. Biphase Input
SIGNAL NAME MPIO GROUP / PIN DESCRIPTION
RXIN8 MPIO_A0 Biphase signal input 8
RXIN9 MPIO_A1 Biphase signal input 9
RXIN10 MPIO_A2 Biphase signal input 10
RXIN11 MPIO_A3 Biphase signal input 11
Table 21. Biphase Output
SIGNAL NAME MPIO GROUP / PIN DESCRIPTION
RECOUT0 MPO0/1 Independent biphase selector 0, output0
RECOUT1 MPO0/1 Independent biphase selector 1, output1
TXOUT MPO0/1 Built-in DIT, biphase output
Table 22. AUX Clocks Output
SIGNAL NAME MPIO GROUP / PIN DESCRIPTION
SBCK MPIO_A0 Secondary bit clock output
SLRCK MPIO_A1 Secondary LR clock output
XMCKO MPIO_A2, MPO0/1 XTI pin input clock buffered output
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