Datasheet
17±1BCK
0L 0R191R
1L 1R 2L 2R
3L
C0L C0RC191R C1L C1R C2L C2R
U0L U0RU191R U1L U1R U2L U2R
RECOVERED
LRCKO(I S)
2
RECOVERED
LRCKO(AllexceptI S)
2
BFRAME
DOUT
COUT
VOUT
L(n) L(n+1)R(n) R(n+1) L(n+2) R(n+2)
V-bit=1
17BCLK
DOUT
VOUT
(RXVDLY=1)
VOUT
(RXVDLY=0)
PCM9211
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SBAS495 –JUNE 2010
Channel Status Data, User Data, and Validity Flag
The PCM9211 can output decoded channel status data, user data, and a validity flag synchronized with audio
data from the input S/PDIF signal. These signals can be transmitted from any of the three MPIOs (MPIO_A,
MPIO_B, or MPIO_C). To assign this function to the MPIOs, see the MPIO section.
Each type of output data has own dedicated output pin:
• Channel status data (C) are output through MPIOs assigned as COUT.
• User data (U) are output through MPIOs assigned as UOUT.
• Validity flag (V) is output through MPIOs assigned as VOUT
• Data (left and right) are identified as DOUT.
C, U, and V output data are synchronized with the recovered LRCKO (left-right clock output) from the S/PDIF
input signal.
The polarity of the recovered LRCKO from the S/PDIF input depends on the Register 2Fh/RXFMT[2:0] setting.
The beginning of each S/PDIF frame (BFRAME) is provided as one of the outputs on the MPIO. It can be used to
indicate the start of the frame to the decoding DSP. If the DIR decodes a start-of-frame preamble on the decoded
data, then it sets BFRAME high for 8xLRCK periods to signify the start of the frame.
LRCKO can be used as a reference clock for each of the data outputs, BFRAME, DOUT, COUT, UOUT, and
VOUT. The relationship between each output is shown in Figure 24.
Numbers 0 to 191 of DOUT, COUT, UOUT, and VOUT in Figure 24 indicate the frame number of the input
biphase signal.
Figure 24. LRCKO, DOUT, BFRAME, COUT, UOUT, and VOUT Output Timing
The RXVDLY Register in Register 22h controls when the VOUT pin goes high (either immediately, or at the start
of the sample/frame). Figure 25 shows these timing sequences.
Figure 25. RXVDLY and VOUT Timing
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