Datasheet

DOUT 0.5V
DD
1.4V
LRCK
(INPUT)
BCK
(INPUT)
1.4V
t
BCH
t
BC L
t
BC Y
t
LRH
t
DOD
t
LRS
PCM9211
SBAS495 –JUNE 2010 www.ti.com
ADC: Audio Interface Mode and Timing
The digital audio data can be interfaced in either slave or master mode. The interface mode is selected by using
the serial mode control described in the Serial Control Mode section. The default mode is slave mode. Master
mode is available only for ADC standalone operation by setting Register 6Fh/MPCSEL. In slave mode, BCK and
LRCK are inputs to the ADC. BCK must be 64f
S
. DOUT changes on the falling edge of BCK. The default timing
specification is shown in Figure 15.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
BCY
BCK Cycle Time 75 ns
t
BCH
BCK High Time 35 ns
t
BCL
BCK Low Time 35 ns
t
LRS
LRCK Set-up Time to BCK Rising Edge 10 ns
t
LRH
LRCK Hold Time to BCK Rising Edge 10 ns
t
DOD
DOUT Delay Time from BCK Falling Edge 10 70 ns
Note: Load capacitance of output is 20 pF. This timing requirement is applied when the ADC is working in standalone mode.
The master mode through MPIO_C ports are set by Register 48h/ADIFMD and Register 6Fh/MPCSEL.
Figure 15. Audio Data Interface Timing (Slave Mode: BCK and LRCK Work as Inputs)
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