Datasheet

PCM9211
www.ti.com
SBAS495 JUNE 2010
Register 7Bh, GPIO Output Data Setting for MPIO_A, MPIO_B
(Address: 7Bh, Write and Read)
DATA B7 B6 B5 B4 B3 B2 B1 B0
Reg Name GPOB3 GPOB2 GPOB1 GPOB0 GPOA3 GPOA2 GPOA1 GPOA0
Default Value 0 0 0 0 0 0 0 0
Memo
GPOB3: MPIO_B3 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
GPOB2: MPIO_B2 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
GPOB1: MPIO_B1 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
GPOB0: MPIO_B0 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
GPOA3: MPIO_A3 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
GPOA2: MPIO_A2 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
GPOA1: MPIO_A1 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
GPOA0: MPIO_A0 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
These registers are effective only as GPIOs are assigned to output.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 113
Product Folder Link(s): PCM9211