Datasheet

PCM9211
www.ti.com SBAS495 –JUNE 2010
Register 79h, GPIO I/O Direction Control for MPIO_A, MPIO_B
(Address: 79h, Write and Read)
DATA B7 B6 B5 B4 B3 B2 B1 B0
Reg Name GIOB3DIR GIOB2DIR GIOB1DIR GIOB0DIR GIOA3DIR GIOA2DIR GIOA1DIR GIOA0DIR
Default Value 0 0 0 0 0 0 0 0
Memo
GIOB3DIR: MPIO_B3 Pin, GPIO I/O Direction Control
0: Input (default)
1: Output
GIOB2DIR: MPIO_B2 Pin, GPIO I/O Direction Control
0: Input (default)
1: Output
GIOB1DIR: MPIO_B1 Pin, GPIO I/O Direction Control
0: Input (default)
1: Output
GIOB0DIR: MPIO_B0 Pin, GPIO I/O Direction Control
0: Input (default)
1: Output
GIOA3DIR: MPIO_A3 Pin Function, GPIO I/O Direction Control
0: Input (default)
1: Output
GIOA2DIR: MPIO_A2 Pin Function, GPIO I/O Direction Control
0: Input (default)
1: Output
GIOA`DIR: MPIO_A1 Pin Function, GPIO I/O Direction Control
0: Input (default)
1: Output
GIOA0DIR: MPIO_A0 Pin Function, GPIO I/O Direction Control
0: Input (default)
1: Output
These registers are effective only at MPIO_A and MPIO_B assigned as GPIO. I/O direction setting is available by
pin.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 111
Product Folder Link(s): PCM9211