Datasheet

PCM9211
SBAS495 –JUNE 2010 www.ti.com
Register 74h, MPIO_B1, MPIO_B0 Output Flag Select
(Address: 74h, Write and Read)
DATA B7 B6 B5 B4 B3 B2 B1 B0
Reg Name MPB1FLG3 MPB1FLG2 MPB1FLG1 MPB1FLG0 MPB0FLG3 MPB0FLG2 MPB0FLG1 MPB0FLG0
Default Value 0 0 0 0 0 0 0 0
Memo
MPB1FLG[3:0]: MPIO_B1 Pin, Flag Select
0000: CLKST (default)
0001: EMPH
0010: BPSYNC
0011: DTSCD
0100: PARITY
0101: LOCK
0110: VOUT
0111: UOUT
1000: COUT
1001: BFRAME
1010: FSOUT0
1011: FSOUT1
1100: FSOUT2
1101: FSOUT3
1110: INT0
1111: INT1
MPB0FLG[3:0]: MPIO_B0 Pin, Flag Select
0000: CLKST (default)
0001: EMPH
0010: BPSYNC
0011: DTSCD
0100: PARITY
0101: LOCK
0110: VOUT
0111: UOUT
1000: COUT
1001: BFRAME
1010: FSOUT0
1011: FSOUT1
1100: FSOUT2
1101: FSOUT3
1110: INT0
1111: INT1
These register settings are effective only at MPBSEL[2:0] = '011', MPB1SEL = '0', and MPB0SEL = '0'.
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