Datasheet

PCM5141, PCM5142
www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012
0: GPIO2 is input
1: GPIO2 is output
G1OE GPIO1 Output Enable
This bit sets the direction of the GPIO1 pin
Default value: 0
0: GPIO1 is input
1: GPIO1 is output
Page 0 / Register 9
Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
9 09 RSV RSV BCKP BCKO RSV RSV RSV LRKO
Reset Value 0 0 0
RSV Reserved
Reserved. Do not access.
BCKP BCK Polarity
This bit sets the inverted BCK mode. In inverted BCK mode, the DAC assumes that the LRCK and DIN edges
are aligned to the rising edge of the BCK. Normally they are assumed to be aligned to the falling edge of the
BCK.
Default value: 0
0: Normal BCK mode
1: Inverted BCK mode
BCKO BCK Output Enable
This bit sets the BCK pin direction to output for I
2
S master mode operation. In I
2
S master mode the PCM51xx
outputs the reference BCK and LRCK, and the external source device provides the DIN according to these
clocks. Use Page 0 / Register 32 to program the division factor of the SCK to yield the desired BCK rate
(normally 64f
S
)
Default value: 0
0: BCK is input (I
2
S slave mode)
1: BCK is output (I
2
S master mode)
LRKO LRCLK Output Enable
This bit sets the LRCK pin direction to output for I
2
S master mode operation. In I
2
S master mode the PCM51xx
outputs the reference BCK and LRCK, and the external source device provides the DIN according to these
clocks. Use Page 0 / Register 33 to program the division factor of the BCK to yield 1f
S
for LRCK.
Default value: 0
0: LRCK is input (I
2
S slave mode)
1: LRCK is output (I
2
S master mode)
Page 0 / Register 10
Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
10 0A DSPG7 DSPG6 DSPG5 DSPG4 DSPG3 DSPG2 DSPG1 DSPG0
Reset Value 0 0 0 0 0 0 0 0
DSPG[7:0] DSP GPIO Input
The DSP accepts a 24-bit external control signals input. The value set in this register will go to bit 16:8 of this
external input.
Default value: 00000000
Page 0 / Register 12
Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
12 0C RSV RSV RSV RSV RSV RSV RBCK RLRK
Reset Value 0 0
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