Datasheet

PCM5141, PCM5142
www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012
RSV Reserved
Reserved. Do not access.
RQML Mute Left Channel
This bit issues soft mute request for the left channel. The volume will be smoothly ramped down or up to avoid
pop or click noise.
Default value: 0
0: Normal volume
1: Mute
RQMR Mute Right Channel
This bit issues soft mute request for the right channel. The volume will be smoothly ramped down or up to
avoid pop or click noise.
Default value: 0
0: Normal volume
1: Mute
Page 0 / Register 4
Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
4 04 RSV RSV RSV PLCK RSV RSV RSV PLLE
Reset Value 1
RSV Reserved
Reserved. Do not access.
PLCK PLL Lock Flag (Read Only)
This bit indicates whether the PLL is locked or not. When the PLL is disabled this bit always shows that the
PLL is not locked. 0: The PLL is locked
1: The PLL is not locked
PLLE PLL Enable
This bit enables or disables the internal PLL. When PLL is disabled, the master clock will be switched to the
SCK.
Default value: 1
0: Disable PLL
1: Enable PLL
Page 0 / Register 6
Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
6 06 RSV RSV RSV RSV RSV RSV FSMI1 FSMI0
Reset Value 0 0
RSV Reserved
Reserved. Do not access.
FSMI[1:0] SPI MISO function sel
These bits select the function of the SPI_MISO pin when in SPI mode. If the pin is set as GPIO, register
readout via SPI is not possible.
Default value: 00
00: SPI_MISO
01: GPIO1
Others: Reserved (Do not set)
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