Datasheet
9
SDA
SCL
St
Start
condition
1–7 8 1–8 9 1–8 9
9
Sp
Stop
condition
Slave address R/W ACK DATA ACK DATA ACK ACK
R/W: Read operation if 1; otherwise, write operation
ACK: Acknowledgement of a byte if 0
DATA: 8 bits (byte)
MSB LSB
INC A6 A5 A4 A3 A2 A1 A0
PCM5141, PCM5142
SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012
www.ti.com
I
2
C Interface
The PCM514x supports the I
2
C serial bus and the data transmission protocol for standard and fast mode as a
slave device. This protocol is explained in the I
2
C specification 2.0.
In I
2
C mode, the control terminals are changed as follows.
Table 48. I
2
C Pins and Functions
Signal Pin I/O Description
SDA 11 I/O I
2
C data
SCL 12 I I
2
C clock
ADR2 16 I I
2
C address 2
ADR1 24 I I
2
C address 1
Slave Address
Table 49. I
2
C Slave Address
MSB LSB
1 0 0 1 1 ADR2 ADR1 R/ W
The PCM514x has 7 bits for its own slave address. The first five bits (MSBs) of the slave address are factory
preset to 10011. The next two bits of the address byte are the device select bits which can be user-defined by
the ADR1 and ADR0 terminals. A maximum of four PCM51xxs can be connected on the same bus at one time.
Each PCM514x responds when it receives its own slave address.
Register Address Auto-Increment Mode
Figure 87. Auto Increment Mode
Auto-increment mode allows multiple sequential register locations to be written to or read back in a single
operation, and is especially useful for block write and read operations.
Packet Protocol
A master device must control packet protocol, which consists of start condition, slave address, read/write bit,
data if write or acknowledge if read, and stop condition. The PCM514x supports only slave receivers and slave
transmitters.
Figure 88. Packet Protocol
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