Datasheet

PCM5141, PCM5142
www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012
Table 42. Ramp Up or Down Frequency (continued)
11 Direct change 11 Direct change
Table 43. Ramp Up or Down Step
Ramp down
Ramp up step Step dB Comments Step dB Comments
step
00 4.0 00 -4.0
01 2.0 01 -2.0
10 1.0 Default 10 -1.0 Default
11 0.5 11 -0.5
Emergency Ramp Down
Digital volume emergency ramp down by is provided for situations such as I
2
S clock error and power supply
failure. Ramp-down speed is controlled by Page 0, Register 64, D(7:6). Ramp-down step can be controlled by
Page 0 Register 64, D(5:4). Default is ramp-down by every f
S
cycle with -4dB step.
Zero Data Detect
The PCM514x has a zero-detect function. When the device detects the continuous zero data for both L-ch and
R-cn, or separate L-cn and R-ch, Analog mutes are set to both OUTL and OUTR, or separate OUTL and OUTR.
These are controlled by Page0, Register 65, D(2:1) as shown in Table 44.
Continuous Zero data cycles are counted by LRCK, and the threshold of decision for analog mute can be set by
Page 0, Register 59, D(6:4) for L-ch, and D(2:0) for Rch as shown in Table 45. Default values are 0 for both
channels.
In Hardware mode, the device uses default values.
Table 44. Zero Detection Mode
ATMUTECTL Value Function
0 Independently L-ch or R-ch are zero data for zero detection
Bit : 2
1 (Default) Both L-ch and R-ch have to be zero data for zero detection
0 Zero detection and analog mute are disabled for R-ch
Bit : 1
1 (Default) Zero detection analog mute are enabled for R-ch
0 Zero detection analog mute are disabled for L-ch
Bit : 0
1 (Default) Zero detection analog mute are enabled for L-ch
Table 45. Zero Data Detection Time
ATMUTETIML /
Number of LRCKs Time @ 48kHz
ATMUTETIMR
0 0 0 1024 21 ms
0 0 1 5120 106 ms
0 1 0 10240 213 ms
0 1 1 25600 533 ms
1 0 0 51200 1.066 sec
1 0 1 102400 2.133 sec
1 1 0 256000 5.333 sec
1 1 1 512000 10.66 sec
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