Datasheet
CPVDD
CAPP
CPGND
CAPM
VNEG
OUTL
OUTR
AVDD
AGND
DEMP
ATT2
ATT1
ATT0
MAST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DVDD
DGND
LDOO
XSMT
FMT
LRCK
DIN
BCK
SCK
FLT
MODE2
MODE1
DOUT
AGNS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PCM5141, PCM5142
SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012
www.ti.com
PCM514x pin assignments-3 MODE1 tied DGND and MODE2 tied DGND : Hardwired mode
PCM514x (top view)
The H/W mode has digital gain and attenuation level control by decoding external ATT2 (11 pin), ATT1 (12 pin),
and ATT0 (pin 13). Table 1 shows the pins used to set gain and attenuation levels.
Table 4. Gain and Attenuation in Hardware Mode
ATT pin condition (ATT2 : ATT1 :
Gain and Attenuation level
ATT0)
( 0 0 0 ) 0 dB
( 0 0 1 ) + 3 dB
( 0 1 0 ) + 6 dB
( 0 1 1 ) + 9 dB
( 1 0 0 ) + 12 dB
( 1 0 1 ) + 15 dB
( 1 1 0 ) - 6 dB
( 1 1 1 ) - 3 dB
Table 5. PCM514x Hardwired mode Terminal Functions
Terminal
I/O Description
Name Pin
CPVDD 1 - Charge pump power supply, 3.3V
CAPP 2 O Charge pump flying capacitor terminal for positive rail
CPGND 3 - Charge pump ground
CAPM 4 O Charge pump flying capacitor terminal for negative rail
VNEG 5 O Negative charge pump rail terminal for decoupling, -3.3V
OUTL 6 O Analog output from DAC left channel
OUTR 7 O Analog output from DAC right channel
AVDD 8 - Analog power supply, 3.3V
AGND 9 - Analog ground
DEMP 10 I De-emphasis control for 44.1kHz sampling rate
(1)
: Off (Low) / On (High)
ATT2 11 I Digital gain and attenuation control pin
(1)
ATT1 12 I Digital gain and attenuation control pin
(1)
ATT0 13 I Digital gain and attenuation control pin
I
2
S Master clock select pin : Master (High) BCK/LRCK outputs, Slave (Low) BCK/LRCK
MAST 14 I
inputs
AGNS 15 I Analog gain selector : 0dB 2V
RMS
output (Low), -6dB 1V
RMS
output (High)
GPO 16 O General Purpose Output (Low level)
(1) Failsafe LVCMOS Schmitt trigger input.
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