Datasheet

CPVDD
CAPP
CPGND
CAPM
VNEG
OUTL
OUTR
AVDD
AGND
VCOM
SDA
SCL
GPIO5
GPIO4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DVDD
DGND
LDOO
XSMT
ADR1
LRCK
DIN
BCK
SCK
GPIO6
MODE2
MODE1
ADR2
GPIO3
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PCM5141, PCM5142
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SLAS759A AUGUST 2012REVISED SEPTEMBER 2012
PCM514x pin assignments-2 MODE1 tied DGND and MODE2 tied DVDD : I
2
C mode
PCM514x (top view)
Table 3. PCM514x I
2
C mode Terminal Functions
TERMINAL
I/O DESCRIPTIONS
NAME PIN
CPVDD 1 - Charge pump power supply, 3.3V
CAPP 2 O Charge pump flying capacitor terminal for positive rail
CPGND 3 - Charge pump ground
CAPM 4 O Charge pump flying capacitor terminal for negative rail
VNEG 5 O Negative charge pump rail terminal for decoupling, -3.3V
OUTL 6 O Analog output from DAC left channel
OUTR 7 O Analog output from DAC right channel
AVDD 8 - Analog power supply, 3.3V
AGND 9 - Analog ground
VCOM output (Optional mode selected by register; default setting is VREF mode.) When
VCOM 10 I in VREF mode (default), this pin ties to GND. When in VCOM mode, decoupling capacitor
to GND is required.
SDA 11 I/O Input data for I
2
C
(1)(2)
SCL 12 I Input clock for I
2
C
(2)
GPIO5 13 I/O General purpose digital input and output port
GPIO4 14 I/O General purpose digital input and output port
GPIO3 15 I/O General purpose digital input and output port
ADR2 16 I 2nd LSB address select bit for I
2
C
MODE1 17 I Mode-control selection pins
(2)
MODE1=Low, MODE2=Low : Hardwired mode
MODE1=Low, MODE2=High : I
2
C mode
MODE2 18 I
MODE1=High : SPI mode, MODE2 pin changes MS pin (chip select
for SPI)
GPIO6 19 I/O General purpose digital input and output port
SCK 20 I System clock input
(2)
BCK 21 I/O Audio data bit clock input (slave) or output (master)
(2)
DIN 22 I Audio data input
(2)
LRCK 23 I/O Audio data word clock input (slave) or output (master)
(2)
ADR1 24 I LSB address select bit for I
2
C
XSMT 25 I Soft mute control : Soft mute (Low) / soft un-mute (High)
(2)
LDOO 26 - Internal logic supply rail terminal for decoupling, 1.8V
DGND 27 - Digital ground
DVDD 28 - Digital power supply, 3.3V or 1.8V
(1) Open-drain configuration in out mode.
(2) Failsafe LVCMOS Schmitt trigger input.
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