Datasheet

PCM5141, PCM5142
www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012
Table 12. Recommended Clock Divider Settings for PLL as Master Clock (VREF Mode) (continued)
PLL VCO DSP CLK
f
S
(kHz) RSCK SCK (MHz) P PLL REF (MHz) M = K*R K = J.D R PLL f
S
DSP f
S
NMAC MOD f
S
MOD f (kHz) NDAC DOSR % Error NCP CP f (kHz)
(MHz) (MHz)
96 48 4.608 98.304 3 1.536 64 32 2 1024 512 2 49.152 64 6144 16 4 0 4 1536
96 64 6.144 98.304 1 6.144 16 8 2 1024 512 2 49.152 64 6144 16 4 0 4 1536
96 128 12.288 98.304 2 6.144 16 16 1 1024 512 2 49.152 64 6144 16 4 0 4 1536
96 192 18.432 98.304 3 6.144 16 16 1 1024 512 2 49.152 64 6144 16 4 0 4 1536
96 256 24.576 98.304 4 6.144 16 16 1 1024 512 2 49.152 64 6144 16 4 0 4 1536
96 384 36.864 98.304 6 6.144 16 16 1 1024 512 2 49.152 64 6144 16 4 0 4 1536
96 512 49.152 98.304 8 6.144 16 16 1 1024 512 2 49.152 64 6144 16 4 0 4 1536
192 32 6.144 98.304 1 6.144 16 8 2 512 256 2 49.152 32 6144 16 2 0 4 1536
192 48 9.216 98.304 3 3.072 32 16 2 512 256 2 49.152 32 6144 16 2 0 4 1536
192 64 12.288 98.304 1 12.288 8 4 2 512 256 2 49.152 32 6144 16 2 0 4 1536
192 128 24.576 98.304 2 12.288 8 8 1 512 256 2 49.152 32 6144 16 2 0 4 1536
192 192 36.864 98.304 3 12.288 8 8 1 512 256 2 49.152 32 6144 16 2 0 4 1536
192 256 49.152 98.304 4 12.288 8 8 1 512 256 2 49.152 32 6144 16 2 0 4 1536
384 32 12.288 98.304 2 6.144 16 8 2 256 128 2 49.152 16 6144 16 1 0 4 1536
384 48 18.432 98.304 3 6.144 16 8 2 256 128 2 49.152 16 6144 16 1 0 4 1536
384 64 24.576 98.304 2 12.288 8 4 2 256 128 2 49.152 16 6144 16 1 0 4 1536
384 128 49.152 98.304 4 12.288 8 8 1 256 128 2 49.152 16 6144 16 1 0 4 1536
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