Datasheet
PCM5141, PCM5142
SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012
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Table 10. PLL Registers
Divider Function Bits
PLLE PLL enable Page 0, Register 4, D(0)
PPDV PLL P Page 0, Register 20, D(3:0)
PJDV PLL J Page 0, Register 21, D(5:0)
Page 0, Register 22, D(5:0)
PDDV PLL D
Page 0, Register 23, D(7:0)
PRDV PLL R Page 0, Register 24, D(3:0)
Table 11. PLL Configuration Recommendations
Column Description
f
S
(kHz) Sampling frequency
RSCK Ratio between sampling frequency and SCK frequency (SCK frequency = RSCK x sampling frequency)
SCK (MHz) System master clock frequency at SCK input (pin 20)
PLL VCO (MHz) PLL VCO frequency as PLLCK in Figure 26
P One of the PLL coefficients in Equation 1
PLL REF (MHz) Internal reference clock frequency which is produced by SCK / P
M = K * R The final PLL multiplication factor computed from K and R as described in Equation 1
K = J.D One of the PLL coefficients in Equation 1
R One of the PLL coefficients in Equation 1
PLL f
S
Ratio between f
S
and PLL VCO frequency (PLL VCO / f
S
)
DSP f
S
Ratio between miniDSP operating clock rate and f
S
(PLL f
S
/ NMAC)
NMAC The miniDSP clock divider value in Table 9
DSP CLK (MHz) The miniDSP operating frequency as DSPCK in Figure 26
MOD f
S
Ratio between DAC operating clock frequency and f
S
(PLL f
S
/ NDAC)
MOD f (kHz) DAC operating frequency as DACCK in Figure 26
NDAC DAC clock divider value in Table 9
OSR clock divider value in Table 9 for generating OSRCK in Figure 26. DOSR must be chosen so that MOD f
S
/ DOSR =
DOSR
16 for correct operation.
NCP NCP (negative charge pump) clock divider value in Table 9
CP f Negative charge pump clock frequency (f
S
* MOD f
S
/ NCP)
Percentage of error between PLL VCO / PLL f
S
and f
S
(mismatch error).
• This number is typically zero but can be non-zero especially when K is not an integer (D is
% Error
not zero).
• This number may be non-zero only when the PCM514xacts as a master.
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