Datasheet
t
SCKH
System Clock
(SCK)
t
SCKL
"L"
"H"
0.3*DVDD
0.7*DVDD
t
SCY
PCM5141, PCM5142
SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012
www.ti.com
System Clock Input
The PCM514x requires a system clock to operate the digital interpolation filters and advanced segment DAC
modulators. The system clock is applied at the SCK input (pin 20) and supports up to 50MHz. The PCM514x
system-clock detection circuit automatically senses the system-clock frequency. Common audio sampling
frequencies of 8kHz, 16kHz, 32kHz - 44.1kHz - 48kHz, 88.2kHz - 96kHz, 176.4kHz -192kHz, and 384kHz with
±4% tolerance are supported. The sampling frequency detector sets the clock for the digital filter, Delta Sigma
Modulator (DSM) and the Negative Charge Pump (NCP) automatically. Table 6 shows examples of system clock
frequencies for common audio sampling rates.
SCK rates that are not common to standard audio clocks, between 1MHz and 50MHz, are only supported in
software mode by configuring various PLL and clock-divider registers. This programmability allows the device to
become a clock master and drive the host serial port with LRCK and BCK, from a non-audio related clock (for
example, using 12MHz to generate 44.1kHz (LRCK) and 2.8224MHz (BCK) ).
Figure 25 shows the timing requirements for the system clock input. For optimal performance, use a clock source
with low phase jitter and noise.
Table 6. System Master Clock Inputs for Audio Related Clocks
System Clock Frequency (f
SCK
) (MHz)
Sampling
Frequency
64 f
S
128 f
S
192 f
S
256 f
S
384 f
S
512 f
S
768 f
S
1024 f
S
1152 f
S
1536 f
S
2048 f
S
3072 f
S
8 kHz –
(1)
1.0240
(2)
1.5360
(2)
2.0480 3.0720 4.0960 6.1440 8.1920 9.2160 12.2880 16.3840 24.5760
16 kHz –
(1)
2.0480
(2)
3.0720
(2)
4.0960 6.1440 8.1920 12.2880 16.3840 18.4320 24.5760 36.8640 49.1520
32 kHz –
(1)
4.0960
(2)
6.1440
(2)
8.1920 12.2880 16.3840 24.5760 32.7680 36.8640 49.1520 –
(1)
–
(1)
44.1 kHz –
(1)
5.6488
(2)
8.4672
(2)
11.2896 16.9344 22.5792 33.8688 45.1584 –
(1)
–
(1)
–
(1)
–
(1)
48 kHz –
(1)
6.1440
(2)
9.2160
(2)
12.2880 18.4320 24.5760 36.8640 49.1520 –
(1)
–
(1)
–
(1)
–
(1)
88.2 kHz –
(1)
11.2896
(2)
16.9344 22.5792 33.8688 45.1584 –
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
96 kHz –
(1)
12.2880
(2)
18.4320 24.5760 36.8640 49.1520 –
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
176.4 kHz –
(1)
22.5792 33.8688 45.1584 –
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
192 kHz –
(1)
24.5760 36.8640 49.1520 –
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
384 kHz 24.5760 49.1520 –
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
(1) This system clock rate is not supported for the given sampling frequency.
(2) This system clock rate is supported by PLL mode.
Figure 25. Timing Requirements for SCK Input
Table 7. Timing Requirements for SCK Input
Parameters Min Max Unit
t
SCY
System clock pulse cycle time 20 1000 ns
DVDD=1.8V 8
t
SCKH
System clock pulse width, High ns
DVDD=3.3V 9
DVDD=1.8V 8
t
SCKL
System clock pulse width, Low ns
DVDD=3.3V 9
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