Datasheet

PCM5121, PCM5122
SLAS763A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com
RSV Reserved
Reserved. Do not access.
DOSR[6:0] OSR Clock Divider
These bits set the source clock divider value for the OSR clock. These bits are ignored in clock auto set mode.
Default value: 0000000
0000000: Divide by 1
0000001: Divide by 2
...
1111111: Divide by 128
Page 0 / Register 32
Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
32 20 RSV DBCK6 DBCK5 DBCK4 DBCK3 DBCK2 DBCK1 DBCK0
Reset Value 0 0 0 0 0 0 0
RSV Reserved
Reserved. Do not access.
DBCK[6:0] Master Mode BCK Divider
These bits set the SCK divider value to generate I
2
S master BCK clock.
Default value: 0000000
0000000: Divide by 1
0000001: Divide by 2
...
1111111: Divide by 128
Page 0 / Register 33
Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
33 21 DLRK7 DLRK6 DLRK5 DLRK4 DLRK3 DLRK2 DLRK1 DLRK0
Reset Value 0 0 0 0 0 0 0 0
DLRK[7:0] Master Mode LRCK Divider
These bits set the I
2
S master BCK clock divider value to generate I
2
S master LRCK clock.
Default value: 00000000
00000000: Divide by 1
00000001: Divide by 2
...
11111111: Divide by 256
Page 0 / Register 34
Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
34 22 RSV RSV RSV RSV RSV RSV FSSP1 FSSP0
Reset Value 0 0 0
RSV Reserved
Reserved. Do not access.
FSSP[1:0] f
S
Speed Mode
These bits select the f
S
operation mode, which must be set according to the current audio sampling rate. These
bits are ignored in clock auto set mode.
Default value: 00
00: Single speed (f
S
= 48 kHz)
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Product Folder Links: PCM5121 PCM5122