Datasheet

BCK
t
BCH
t
BCL
t
BCY
t
DS
t
DH
t
LRD
DATA
LRCK
0. 5 * DVDD
0. 5 * DVDD
0. 5 * DVDD
( Output)
( Output)
( Output)
t
DOD
DATA 0. 5 * DVDD
(Input)
PCM5141, PCM5142
www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012
The I
2
S master timing is shown in Figure 28 and Table 18.
Figure 28. PCM514x Serial Audio Timing - Master
Table 18. Audio Interface Master Timing
Parameters Min Max Units
t
BCY
BCK Pulse Cycle Time 40 ns
t
BCL
BCK Pulse Width LOW 16 ns
t
BCH
BCK Pulse Width HIGH 16 ns
t
BCK
BCK frequency at DVDD = 3.3V 24.576 MHz
t
BCK(1.8V)
BCK frequency at DVDD = 1.8V 12.288 MHz
t
LRD
LRCKx delay time from BCKx falling edge –10 20 ns
t
DS
DATA Set Up Time 8 ns
t
DH
DATA Hold Time 8 ns
DATA delay time from BCK falling edge at DVDD
t
DOD
15 ns
= 3.3V
DATA delay time from BCK falling edge at DVDD
t
DOD(1.8V)
20 ns
= 1.8V
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