Datasheet
CPVDD
CAPP
CPGND
CAPM
VNEG
OUTL
OUTR
AVDD
AGND
VCOM
MOSI
MC
GPIO5
GPIO4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DVDD
DGND
LDOO
XSMT
MISO
LRCK
DIN
BCK
SCK
GPIO6
MS
MODE1
GPIO2
GPIO3
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PCM5141, PCM5142
www.ti.com
SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012
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DEVICE INFORMATION
PCM514x pin assignments-1 MODE1 tied DVDD : SPI mode
PCM514x (top view)
Table 2. PCM514x SPI mode Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME PIN
CPVDD 1 - Charge pump power supply, 3.3V
CAPP 2 O Charge pump flying capacitor terminal for positive rail
CPGND 3 - Charge pump ground
CAPM 4 O Charge pump flying capacitor terminal for negative rail
VNEG 5 O Negative charge pump rail terminal for decoupling, -3.3V
OUTL 6 O Analog output from DAC left channel
OUTR 7 O Analog output from DAC right channel
AVDD 8 - Analog power supply, 3.3V
AGND 9 - Analog ground
VCOM output (Optional mode selected by register; default setting is VREF mode.) When in
VCOM 10 O VREF mode (default), this pin ties to GND. When in VCOM mode, decoupling capacitor to
GND is required.
MOSI 11 I Input data for SPI
(1)
MC 12 I Input clock for SPI
(1)
GPIO5 13 I/O General purpose digital input and output port
GPIO4 14 I/O General purpose digital input and output port
GPIO3 15 I/O General purpose digital input and output port
GPIO2 16 I/O General purpose digital input and output port
MODE1 17 I Mode control selection pin
(1)
• MODE1=Low, MODE2=Low : Hardwired mode
• MODE1=Low, MODE2=High : I
2
C mode
MS (MODE2) 18 I
• MODE1=High : SPI mode, MODE2 pin changes MS pin (chip select for
SPI)
GPIO6 19 I/O General purpose digital input and output port
SCK 20 I System clock input
(1)
BCK 21 I/O Audio data bit clock input (slave) or output (master)
(1)
DIN 22 I Audio data input
(1)
LRCK 23 I/O Audio data word clock input (slave) or output (master)
(1)
Primary output data for SPI readback
MISO (GPIO1) 24 I/O
Secondary; general purpose digital input/output port controlled by register
XSMT 25 I Soft mute control
(1)
Soft mute (Low) / soft un-mute (High)
(1) Failsafe LVCMOS Schmitt trigger input.
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Product Folder Links: PCM5141 PCM5142