Datasheet

SCK
BCK
OSC
GPIO
SRCREF
PLL
K * R / P
K = J.D
J = 1,2,3,..,62,63
D = 0000, 0001,., 9998,9999
R = 1,2,3,4,.,15,16
P = 1,2,.,127,128
PLLCK
MCK
SCK
BCK
OSCCK
PLLCK
SRCDAC
Q=1,2,3,..,127,128
GPIO
DIV
Q
DSPCK
Q=1,2,3,..,127,128
DIV
Q
SCK
PLLEN
Q=1,2,3,..,127,128
DIV
Q
DACCK
CPCK
Q=1,2,3,..,127,128
DIV
Q
OSRCK
DIV
Q
OFSCCK
OSCCK
Q=1,2,3,..,127,128
DIV
Q
BCKO
SCK
Q=1,2,3,..,127,128
DIV
Q
LRCKO
Q=1,2,3,..,127,128
PLLCKIN
PCM5141, PCM5142
SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com
Table 9. PLL Configuration Registers (continued)
DLRK External LRCK Div Page 0, Register 33, D(7:0)
Figure 26. PLL Clock Source and Clock Distribution
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