Datasheet

XSMT
0.9 * DV
DD
t
r
t
f
<20ns
<20ns
0.1 * DV
DD
PCM5100, PCM5101, PCM5102
SLAS764B –MAY 2011–REVISED SEPTEMBER 2012 www.ti.com
Zero Data Detect
The PCM510x has a zero-data detect function. When the device detects continuous zero data, it enters a full
analog mute condition.
The PCM510x counts zero data over 1024LRCKs (21ms @ 48kHz) before setting analog mute.
Power Save Mode
When any kind of clock error (SCK, BCK, and LRCK) or clock halt is detected, the PCM510x enters Stand-by
mode automatically. The current-segment DAC and Line driver are also powered down.
When BCK and LRCK halt to a low level for more than 1 second, the PCM510x enters Power down mode
automatically. Power-down mode includes the negative charge pump and Bias/Reference circuit power-down in
addition to stand-by.
Whenever expected Audio clocks (SCK, BCK, LRCK) are applied to the PCM510x, the device starts its powerup
sequence automatically.
XSMT Pin (Soft Mute and Soft Un-Mute)
For external digital control of the PCM510x, the XSMT pin must be driven by an external digital host with a
specific/minimum rise time (t
r
) and fall time (t
f
) for soft mute and soft un-mute. The PCM510x requires t
r
/t
f
times
of less than 20ns. In the majority of applications, this shouldn’t be a problem, however, traces with high
capacitance may have issues.
When the XSMT pin is shifted from high to low (3.3V to 0V), a soft digital attenuation ramp is started. –1dB
attenuation will be applied every 1t
S
from 0dBFS to –∞. This attenuation takes 104 sample times.
When the XSMT pin is shifted from low to high (0V to 3.3V), a soft digital “un-mute” is started. 1dB gain steps are
applied every t
S
from –∞ to 0dBFS. This ramp-up takes 104 sample times.
Figure 34. XSMT Timing for Soft Mute and Soft Un-Mute
Table 15. XSMT Timing Parameters
Parameters Min Max Unit
Rise time (t
r
) 20 ns
Fall time (t
f
) 20 ns
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