Datasheet

PCM5100, PCM5101, PCM5102
SLAS764B –MAY 2011–REVISED SEPTEMBER 2012 www.ti.com
System Clock PLL Mode
The system clock PLL mode allows designers to use a simple 3-wire I
2
S audio source when driving the DAC.
The 3-wire source reduces the need for a high frequency SCK, making PCB layout easier, and reduces high
frequency electromagnetic interference.
The device starts up expecting an external SCK input, but if BCK and LRCK start correctly while SCK remains at
ground level for 16 successive LRCK periods, then the internal PLL starts, automatically generating an internal
SCK from the BCK reference. The PCM510x disables the internal PLL when an external SCK is supplied;
specific BCK rates are required to generate an appropriate master clock. Table 5 describes the minimum and
maximum BCK per LRCK for the integrated PLL to automatically generate an internal SCK.
Table 5. BCK Rates (MHz) by LRCK Sample Rate for
PCM510x PLL Operation
BCK (f
S
)
Sample f (kHz) 32 64
8 - -
16 - 1.024
32 1.024 2.048
44.1 1.4112 2.8224
48 1.536 3.072
96 3.072 6.144
192 6.144 12.288
384 12.288 24.576
Audio Data Interface
Audio Serial Interface
The audio interface port is a 3-wire serial port, including LRCK (pin 15), BCK (pin 13), and DIN (pin 14). BCK is
the serial audio bit clock, used to clock the serial data present on DIN into the serial shift register of the audio
interface. Serial data is clocked into the PCM510x on the rising edge of BCK. LRCK is the serial audio left/right
word clock.
Table 6. PCM510x Audio Data Formats, Bit Depths and Clock Rates
MAX LRCK
CONTROL MODE FORMAT DATA BITS SCK RATE [x f
S
] BCK RATE [x f
S
]
FREQUENCY [f
S
]
128 – 3072
Up to 192kHz 64, 48, 32
(≤50MHz)
Hardware Control I
2
S/LJ 32, 24, 20, 16
384kHz 64, 128 64, 48, 32
The PCM510x requires the synchronization of LRCK and system clock, but does not need a specific phase
relation between LRCK and system clock.
If the relationship between LRCK and system clock changes more than ±5 SCK, internal operation is initialized
within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between
LRCK and system clock is completed.
If the relationship between LRCK and BCK are invalid more than 4 LRCK periods, internal operation is initialized
within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between
LRCK and BCK is completed.
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Product Folder Links: PCM5100 PCM5101 PCM5102