Datasheet

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PCM4222
Dividedby2
MCKI
BCK
LRCK
DIX4192
or
SRC4392
512f (Normal)
S
256f (DoubleSpeed)
S
128f (QuadSpeed)
S
Master
Clock
MCLK
DATA
BCKA
LRCKA
SDINA
PCM4222
SBAS399A – OCTOBER 2006 – REVISED MARCH 2007
VDDPCM4222 = VIODIX4192 or SRC4392.
Audio data format if I
2
S or Left Justified.
Interface supports ADC Slave or Master configurations, depending on DIX4192, SRC4382, or SRC4392 register
setup.
Figure 54. Interfacing the PCM4222 to a DIT4192 , SRC4382 , or SRC4392
Table 12. Register Configuration Sequence for an ADC Master Mode Interface
REGISTER ADDRESS (hex) REGISTER DATA (hex) COMMENTS
7F 00 Select Register Page 0
00 Port A is Slave mode with Left-Justified audio data format, or
03
01 Port A is Slave mode with I
2
S Data format
04 00 Default for Port A Slave mode operation
64 Divide MCLK by 512 for Normal sampling,or
07 24 Divide MCLK by 256 for Double Speed Sampling, or
04 Divide MCLK by 128 for Quad Speed sampling
08 00 Line Driver and AESOUT buffer enabled
Data buffers on Register Page 2 are the source for the DIT
09 01
channel status (C) and user (U) data
01 34 Power up Port A and the DIT
Table 13. Register Configuration Sequence for an ADC Slave Mode Interface
REGISTER ADDRESS (hex) REGISTER DATA (hex) COMMENTS
7F 00 Select Register Page 0
08 Port A is Master mode with Left-Justified audio data format, or
03
09 Port A is Master mode with I
2
S Data format
03 Divide MCLK by 512 for Normal sampling, or
04 01 Divide MCLK by 256 for Double Speed sampling, or
00 Divide MCLK by 128 for Quad Speed sampling
64 Divide MCLK by 512 for Normal sampling,or
07 24 Divide MCLK by 256 for Double Speed Sampling, or
04 Divide MCLK by 128 for Quad Speed sampling
08 00 Line Driver and AESOUT buffer enabled
Data buffers on Register Page 2 are the source for the DIT
09 01
channel status (C) and user (U) data
01 34 Power up Port A and the DIT
34
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