Datasheet

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MASTER CLOCK INPUT

RESET AND POWER-DOWN OPERATION

40nsminimum

RST

Internal

Reset

MCKI

1024SystemClockPeriods

RequiredforInitialization

PCM4222

SBAS399A – OCTOBER 2006 – REVISED MARCH 2007

PRODUCT INFORMATION (continued)

The PCM4222 requires a master clock for operating the internal logic and modulator circuitry. The master clock

is supplied from an external source, connected at the MCKI input (pin 35). Table 1 summarizes the requirements

for various operating modes of the PCM4222. Referring to Table 1 , the term f

refers to the PCM4222 PCM

output sampling rate (that is, 48kHz, 96kHz, 192kHz, etc.). Refer to the Electrical Characteristics table for timing

specifications related to the master clock input, as well as the output sampling and data rates for the PCM, DSD,

and multi-bit output modes.

For best performance, the master clock jitter should be maintained below 40ps peak amplitude.

Table 1. Master Clock Requirements

OPERATING MODE REQUIRED MASTER CLOCK (MCKI) RATE

PCM Normal 256f

PCM Double Speed 128f

PCM Quad Speed 64f

DSD with 64x output rate 4x the desired DSD output rate

DSD with 128x output rate 2x the desired DSD output rate

Multi-bit modulator (MBM) 2x the desired modulator output rate

The PCM4222 includes an external reset input, RST (pin 36), which may be utilized to force an internal reset

initialization or power down sequence. The reset input is active low. Figure 40 shows the required timing for an

external forced reset.

A power-down state for the PCM422 may be initiated by forcing and holding the reset input low for the duration

of the desired power-down condition. Minimum power is consumed during this state when all clock inputs for the

PCM4222 are forced low. Before releasing the reset input by forcing a high state, the master clock should be

enabled so that the PCM4222 can execute a reset initialization sequence.

While the RST pin is forced low, or during reset initialization, the audio data and clock outputs are driven to fixed

states. The following is a summary of the PCM, DSD, and Multi-Bit Modulator audio interfaces. The conditions

noted assume that the given interface has been enabled (that is, PCMEN, DSDEN, or MODEN forced high).

• For PCM mode, the audio serial port LRCK, BCK and DATA are driven low if the port is configured for

Master mode operation. For Slave mode, the DATA pin is forced low.

• For DSD mode, the DSDL, DSDR, and DSDCLK outputs are driven low.

• For the Multi-Bit Modulator (or MBM) mode, the WCKO, MCKO, and MOD1–MOD6 outputs are all driven

low.

Figure 40. External Reset Sequence

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