Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) Internal TQFP 48

PCM4220

Dividedby2

MCKI

BCK

LRCK

DIX4192

SRC4392

512f (Normal)

256f (DoubleSpeed)

128f (QuadSpeed)

Master

Clock

MCLK

DATA

BCKA

LRCKA

SDINA

PCM4220

SBAS407C – DECEMBER 2006 – REVISED AUGUST 2009 .............................................................................................................................................

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NOTE: VDDPCM4220 = VIODIX4192 or SRC4392.

Audio data format if I

S or Left Justified.

Interface supports ADC Slave or Master configurations, depending on DIX4192, SRC4382, or SRC4392 register setup.

Figure 49. Interfacing the PCM4220 to a DIX4192 , SRC4382 , or SRC4392

Table 8. Register Configuration Sequence for an ADC Master Mode Interface

7F 00 Select Register Page 0

00 Port A is Slave mode with Left-Justified audio data format, or

01 Port A is Slave mode with I

S Data format

04 00 Default for Port A Slave mode operation

64 Divide MCLK by 512 for Normal sampling, or

07 24 Divide MCLK by 256 for Double Speed Sampling, or

04 Divide MCLK by 128 for Quad Speed sampling

08 00 Line Driver and AESOUT buffer enabled

Data buffers on Register Page 2 are the source for the DIT channel

09 01

status (C) and user (U) data

01 34 Power up Port A and the DIT

Table 9. Register Configuration Sequence for an ADC Slave Mode Interface

7F 00 Select Register Page 0

08 Port A is Master mode with Left-Justified audio data format, or

09 Port A is Master mode with I

S Data format

03 Divide MCLK by 512 for Normal sampling, or

04 01 Divide MCLK by 256 for Double Speed sampling, or

00 Divide MCLK by 128 for Quad Speed sampling