Datasheet

INTERFACING TO DIGITAL AUDIO TRANSMITTERS (AES3, IEC60958-3, and S/PDIF)
PCM4220
Dividedby2
FS1
LO
LO
HI
HI
FS0
LO
HI
LO
HI
Mode
Normal
DoubleSpeed
QuadSpeed
Reserved
MCKI BCK
LRCK
FS1
FS0
MCLK
CLK0
CLK1
512f (Normal)
S
256f (DoubleSpeed)
S
128f (QuadSpeed)
S
DIT4192
Master
Clock
DATA
S/M
SCLK
SYNC
SDATA
M/S
LO= ADCMaster
HI= ADCSlave
CLK1
LO
LO
HI
HI
CLK0
LO
HI
LO
HI
Mode
QuadSpeed
DoubleSpeed
Reserved
Normal
PCM4220
www.ti.com ............................................................................................................................................. SBAS407C – DECEMBER 2006 – REVISED AUGUST 2009
The serial output of audio analog-to-digital converters is oftentimes interfaced to transmitter devices that encode
the serial output data to either the AES3 or IEC60958-3 (or S/PDIF) interface formats. Texas Instruments
manufactures several devices that perform this encoding, including the DIT4192 , DIX4192 , SRC4382 , and
SRC4392 . This section describes and illustrates the audio serial port interface connections required for
communications between the PCM4220 and these devices. Register programming details for the DIX4192 and
SRC4382/4392 are also provided.
Figure 48 shows the interface between a PCM4220 and a DIT4192 transmitter. This configuration supports
sampling frequencies and encoded frame rates from 8kHz to 216kHz. For this example, the audio data format
must be either Left-Justified or I
2
S; TDM formats are not supported by the DIT4192. In addition, the PCM4220
VDD supply and DIT4192 VIO supply must be the same voltage, to ensure logic level compatibility.
Figure 49 illustrates the audio serial port interface between the PCM4220 and either a DIX4192 transceiver or
SRC4382/SRC4392 combo sample rate converter/transceiver device. Port A of the DIX4192 or
SRC4382/SRC4392 is utilized for this example. Data acquired by Port A are sent on to the DIT function block
within the interface device for AES3 encoding and transmission.
The DIX4192 and SRC4382/SRC4392 are software-configurable, with control register and data buffer settings
that determine the operation of internal function blocks. Table 8 and Table 9 summarize the control register
settings for the Port A and the DIT function blocks for both A/D Converter Master and Slave modes, respectively.
Input sampling and encoded frame rates from 8kHz to 216kHz are supported with the appropriate register
settings.
Figure 48. Interfacing the PCM4220 to a DIT4192
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Product Folder Link(s): PCM4220