Datasheet

DIGITAL HIGH-PASS FILTER
PCM OUTPUT WORD LENGTH REDUCTION
OVERFLOW INDICATORS
PCM4220
www.ti.com ............................................................................................................................................. SBAS407C – DECEMBER 2006 – REVISED AUGUST 2009
The Low Group Delay response provides a lower latency option for the decimation filter, and is detailed in
Figure 28 through Figure 31 , with the relevant specifications given in the Electrical Characteristics table. The Low
Group Delay filter response is available for all sampling modes. The group delay for this filter is 21/f
S
, or 437.5 µ s
for f
S
= 48kHz, 218.75 µ s for f
S
= 96kHz, and 109.375 µ s for f
S
= 192kHz.
The decimation filter response is selected using the DF input (pin 21), with the settings summarized in Table 5 .
For Quad Speed sampling mode operation, the Low Group Delay filter is always selected, regardless of the DF
pin setting.
Table 5. Decimation Filter Response Selection
DF (pin 21) DECIMATION FILTER RESPONSE
LO Classic response, with group delay = 39/f
S
HI Low Group Delay response, with group delay = 21/f
S
The PCM4220 incorporates digital high-pass filters for both the left and right audio channels, with the purpose of
removing the Δ Σ modulator dc offset from the audio output data. Figure 32 and Figure 33 detail the frequency
response for the digital high-pass filter. The f
– 3dB
frequency is approximately f
S
/48000, where f
S
is the PCM
output sampling rate.
Two inputs, HPFDR (pin 17) and HPFDL (pin 18), allow the digital high-pass filter to be enabled or disabled
individually for the right and left channels, respectively. Table 6 summarizes the operation of the high-pass filter
disable pins.
Table 6. Digital High-Pass Filter Configuration
HPFDR (pin 17) or HPFDL (pin 18) HIGH-PASS FILTER STATE
LO Enabled for the corresponding channel
HI Disabled for the corresponding channel
The PCM4220 is typically configured to output 24-bit linear PCM audio data. However, internal word length
reduction circuitry may be utilized to reduce the 24-bit data to 20-, 18-, or 16-bit data. This reduction is
accomplished by using a Triangular PDF dithering function. The OWL0 (pin 42) and OWL1 (pin 41) inputs are
utilized to select the output data word length. Table 7 summarizes the output word length configuration options.
Table 7. PCM Audio Data Word Length Selection
OWL1 (pin 41) OWL0 (pin 42) OUTPUT WORD LENGTH
LO LO 24 bits
LO HI 18 bits
HI LO 20 bits
HI HI 16 bits
The PCM4220 includes two active-high digital overflow outputs, OVFL (pin 37) and OVFR (pin 38),
corresponding to the left and right channels, respectively. These outputs are functional when the PCM output
mode is enabled, as the overflow detection circuitry is incorporated into the digital filter engine. The overflow
indicators are forced high whenever a digital overflow is detected for a given channel. The overflow indicators
may be utilized as clipping flags, and monitored using a host processor or light-emitting diode (LED) indicators.
When driving a LED, the overflow output may be buffered to ensure adequate drive for the LED. A recommended
buffer is Texas Instruments' SN74LVC1G125 . Equivalent buffers may be substituted
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