Datasheet

LRCK
PCM4220 PCM4220
AudioDSP
or
Interface
AudioDSP
or
Interface
BCK
DATA
LRCK
BCK
DATA
MCKI MCLK MCKI MCLK
Master
Clock
Master
Clock
(a)SlaveMode(S/M=HI) (b)MasterMode(S/M=LO)
FSYNC
SCLK
DATA
FSYNC
SCLK
DATA
PCM4220
SBAS407C – DECEMBER 2006 – REVISED AUGUST 2009 ............................................................................................................................................. www.ti.com
For the I
2
S and Left-Justified data formats, the BCK clock output rate is fixed in Master mode, with the Normal
mode being 128f
S
and the Double and Quad Speed modes being 64f
S
. In Slave Mode, a BCK clock input rate of
64f
S
or 128f
S
is recommended for Normal mode, while 64f
S
is recommended for Double and Quad Rate modes.
For the TDM data formats, the BCK rate depends upon the sampling mode for either Slave or Master operation.
For Normal sampling, the BCK must be 256f
S
. Double Speed mode requires 128f
S
, while Quad Speed mode
requires 64f
S
. This requirement limits the maximum number of channels carried by the TDM formats to eight for
Normal mode, four for Double Rate mode, and two for Quad Rate mode.
When using the TDM formats, the sub-frame assignment for the device must be selected using the SUB0 and
SUB1 inputs (pins 26 and 25, respectively). Table 4 summarizes the sub-frame selection options. A sub-frame
contains two 32-bit time slots, with each time slot carrying 24 bits of audio data corresponding to either the left or
right channel of the PCM4220. Refer to Figure 41 through Figure 43 for TDM interfacing connections and
sub-frame formatting details. For the TDM format with one BCK delay, the serial data output is delayed by one
BCK period after the rising edge of the LRCK clock.
Table 4. TDM Sub-frame Assignment
SUB1 (pin 25) SUB0 (pin 26) SUB-FRAME ASSIGNMENT
LO LO Sub-frame 0
LO HI Sub-frame 1
HI LO Sub-frame 2
HI HI Sub-frame 3
When using TDM formats with Double Speed sampling, it is recommended that the SUB1 pin be forced low.
When using TDM formats with Quad Speed sampling, it is recommended that both the SUB0 and SUB1 pins be
forced low.
For all serial port modes and data formats, when driving capacitive loads greater than 30pF with the data and
clock outputs, it is recommended that external buffers be utilized to ensure data and clock integrity at the
receiving device(s).
For specifications regarding audio serial port operation, the reader is referred to the Electrical Characteristics :
Audio Interface Timing table, as well as Figure 1 and Figure 2 in this data sheet.
Figure 39. Slave and Master Mode Operation
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Product Folder Link(s): PCM4220