Datasheet

PCM OUTPUT AND SAMPLING MODES
AUDIO SERIAL PORT INTERFACE
PCM4220
www.ti.com ............................................................................................................................................. SBAS407C – DECEMBER 2006 – REVISED AUGUST 2009
The PCM4220 supports 24-bit linear PCM output data when the PCMEN input (pin 16) is forced high. The PCM
output is disabled when PCMEN is forced low. The 24-bit output data may be dithered to 20-, 18-, or 16-bits
using internal word length reduction circuitry. Refer to the Output Word Length Reduction section of this data
sheet for additional information.
The PCM4220 supports three PCM sampling modes, referred to as Normal, Double Speed, and Quad Speed.
The sampling mode is determined by the state of the FS0 and FS1 inputs (pins 19 and 20, respectively). Table 2
summarizes the sampling modes available for the PCM4220.
Normal sampling mode supports output sampling rates from 8kHz to 54kHz. The Δ Σ modulator operates with
128x oversampling in this mode. Both the Classic and Low Group Delay decimation filter responses are available
in Normal mode. The master clock (MCKI) rate must be 256x the desired output sampling rate for Normal
operation.
The Double Speed sampling mode supports output sampling rates from 54kHz to 108kHz. The delta-sigma
modulator operates with 64x oversampling in this mode. Both the Classic and Low Group Delay decimation filter
responses are available in Double Speed mode. The master clock (MCKI) rate must be 128x the desired output
sampling rate for Double Speed operation.
Quad Speed sampling mode supports output sampling rates from 108kHz to 216kHz. The delta-sigma modulator
operates with 32x oversampling in this mode. Only the Low Group Delay decimation filter response is available in
Quad Speed mode. The master clock (MCKI) rate must be 64x the desired output sampling rate for Quad Speed
operation.
Table 2. PCM Sampling Mode Configuration
FS1 (pin 20) FS0 (pin 19) SAMPLING MODE
LO LO Normal, 8kHz ≤ f
S
≤ 54kHz
LO HI Double Speed, 54kHz < f
S
≤ 108kHz
HI LO Quad Speed, 108kHz < f
S
≤ 216kHz
HI HI Reserved
The PCM output mode supports a three-wire synchronous serial interface. This interface includes a serial data
output (DATA, pin 32), a serial bit or data clock (BCK, pin 33), and a left/right word clock (LRCK, pin 34). The
BCK and LRCK clock pins may be inputs or outputs, depending on the Slave or Master mode configuration.
Figure 39 illustrates Slave and Master mode serial port connections to an external audio signal processor or host
device.
The audio serial port supports four data formats that are illustrated in Figure 40 , Figure 42 , and Figure 43 . The
I
2
S and Left-Justified formats support two channels of audio output data. The TDM data formats can support up
to eight channels of audio output data on a single data line. The audio data format is selected using the FMT0
and FMT1 inputs (pins 44 and 43, respectively). Table 3 summarizes the audio data format options. For all
formats, audio data are represented as two ’ s complement binary data, with the MSB transmitted first. Regardless
of the format selection, audio data are always clocked out of the port on the falling edge of the BCK clock.
Table 3. PCM Audio Data Format Selection
FMT1 (pin 43) FMT0 (pin 44) AUDIO DATA FORMAT
LO LO Left-Justified
LO HI I
2
S
HI LO TDM
HI HI TDM with data delayed one BCK cycle from LRCK rising edge
The LRCK clock rate should always be operated at the desired output sampling rate, or f
S
. In Slave mode, the
LRCK clock is an input, with the rate set by an external audio bus master (that is, a clock generator, digital signal
processor, etc.). In Master mode, the LRCK clock is an output, derived from the master clock input using on-chip
clock dividers (as is the BCK clock). The clock divider is configured using the FS0 and FS1 pins, which are
discussed in the PCM Output and Sampling Modes section of this datasheet.
Copyright © 2006 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): PCM4220