Datasheet

MASTER CLOCK INPUT
RESET AND POWER-DOWN OPERATION
40nsminimum
RST
0V
0V
0V
Internal
Reset
MCKI
1024SystemCLockPeriods
RequiredforInitialization
DISABLED STATES FOR THE PCM4220 AUDIO SERIAL PORT
PCM4220
SBAS407C – DECEMBER 2006 – REVISED AUGUST 2009 ............................................................................................................................................. www.ti.com
The PCM4220 requires a master clock for operating the internal logic and modulator circuitry. The master clock
is supplied from an external source, connected at the MCKI input (pin 35). Table 1 summarizes the requirements
for various operating modes of the PCM4220. Referring to Table 1 , the term f
S
refers to the PCM4220 PCM
output sampling rate (that is, 48kHz, 96kHz, 192kHz, etc.). Refer to the Electrical Characteristics table for timing
specifications related to the master clock input.
For best performance, the master clock jitter should be maintained below 40ps peak amplitude.
Table 1. Master Clock Requirements
OPERATING MODE REQUIRED MASTER CLOCK (MCKI) RATE
PCM Normal 256f
S
PCM Double Speed 128f
S
PCM Quad Speed 64f
S
The PCM4220 includes an external reset input, RST (pin 36), which may be utilized to force an internal reset
initialization or power-down sequence. The reset input is active low. Figure 38 shows the required timing for an
external forced reset.
A power-down state for the PCM422 may be initiated by forcing and holding the reset input low for the duration
of the desired power-down condition. Minimum power is consumed during this state when all clock inputs for the
PCM4220 are forced low. Before releasing the reset input by forcing a high state, the master clock should be
enabled so that the PCM4220 can execute a reset initialization sequence.
While the RST pin is forced low, or during reset initialization, the audio serial port data and clock outputs are
driven low.
Figure 38. External Reset Sequence
When PCMEN (pin 16) is driven low, the PCM output is disabled. The audio serial port data and clocks are
driven low.
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