Datasheet

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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
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24
1024 System Clock Periods
Required for Initialization
SCKI
Internal
Reset
0V
0V
0V
t
RSTL
> 40ns
RST
Figure 12. External Reset Sequence
Internal
Reset
Output
Data Pins
Valid Output Data
Outputs are Forced Low
for 1024 SCKI Periods
Valid Output DataOutputs are Forced Low
Initialization
Period
HI
LO
Figure 13. ADC Digital Output State for Reset Operations