Datasheet

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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
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DSD DATA PORT OPERATION
The DSD data port consists of a single DSD data clock
signal, DSDCLK (pin 24), along with four synchronous
DSD data lines, DSD1 (pin 25), DSD2 (pin 26), DSD3 (pin
27), and DSD4 (pin 28). The data lines correspond to
Channels 1 through 4, respectively. The DSD output or
input data rate is determined by the sampling mode
settings for the device, discussed in the Sampling Modes
section of this datasheet.
For DSD output data, the serial port is configured in Master
mode, with the DSDCLK derived from the system clock
input, SCKI. The DSDCLK is equivalent to the
oversampling clock supplied to the delta-sigma
modulators. The DSD data outputs, DSD1 through DSD4,
are synchronous to the DSDCLK. The clock and data lines
are then connected to a data capture device for storage
and processing.
The DSD input mode, the data port is configured as an
input port, with DSD clock and data lines driven from an
external data source. The Audio Serial Port is configured
in Master mode, with the LRCK and BCK clocks derived
from the system clock input, SCKI. The PCM data format
is set to 24-bit Right-Justified. The input data is processed
by the digital decimation filter and output as PCM data at
the audio serial port.
Figure 10 illustrates the DSD port timing for both the DSD
output and input modes.
HIGH-PASS FILTER
A digital high-pass filter is available for removing the DC
component of the digitized input signal. The filter is located
at the output of the digital decimation filter, and is available
only when using PCM output data formats. The high-pass
filter can be enabled or disabled for all four channels using
the HPFD input (pin 38). Driving the HPFD input low
enables the high-pass filter. Driving the HPFD input high
disables the high-pass filter.
The −3dB corner frequency for the high-pass filter scales
with the output sampling rate, where f
−3dB
= f
S
/48000,
where f
S
is the output sampling rate.
CLIPPING FLAGS
The PCM4204 includes a clipping flag output for each
channel. The outputs are designated CLIP1 (pin 34),
CLIP2 (pin 35), CLIP3 (pin 36), and CLIP4 (pin 37),
corresponding to Channels 1 through 4, respectively.
A clipping flag is forced high as soon as the digital output
of the decimation filter exceeds the full-scale range for the
corresponding channel. The clipping flag output is held
high for a maximum of (256 x N) / f
S
seconds, where N =
128 for Single Rate sampling mode, 256 for Dual Rate
sampling mode, and 512 for Quad Rate sampling mode.
If the decimation filter output does not exceed the full-scale
range during the initial hold period, the output returns to a
low state upon termination of the hold period.
Output
t
DS
t
DH
PARAMETER
DESCRIPTION MIN MAX UNITS
156
70
1010
ns
ns
ns
t
DCKDO
DSDCLK
Input
DSD1
DSD2
DSD3
DSD4
DSD1
DSD2
DSD3
DSD4
t
DCKHL
t
DCKP
DSDCLK Cycle Time
t
DCKP
t
DCKHL
t
DS
DSDCLK High/Low Time
Data Setup Time
1010
ns
t
DH
Data Hold Time
10
ns
t
DCKDO
DSD Data Output Delay from DSDCLK Falling
Figure 10. DSD Data Port Timing