Datasheet

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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
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In Slave mode, the BCK and LRCK signals are inputs, with
the clocks being generated by a master timing source,
such as a DSP serial port, PLL clock synthesizer, or a
crystal oscillator/divider circuit. For Left Justified, Right
Justified, and I
2
S data formats, the BCK rate is typically
128f
S
in Single Rate sampling mode, and 64f
S
in Dual or
Quad Rate sampling modes. Although other BCK clock
rates are possible, they are not recommended due to the
potential for clock phase sensitivity issues, which may
degrade the dynamic performance of the PCM4204. The
LRCK clock operates at f
S
, the output sampling rate.
Figure 6 illustrates the typical audio serial port
connections between a PCM4204 and an audio signal
processor when using Left-Justified, Right-Justified, and
I
2
S data formats in either Slave or Master modes.
LRCK
BCK
SDOUT1
SDOUT2
FSR
CLKR
DR0
DR1
System Clock
PCM4204
DSP
SCKI
Figure 6. Typical Audio Serial Port Connections
for Left-Justified, Right-Justified, and Philips I
2
S
Data Formats
In Slave mode, the TDM data formats support a BCK clock
rate of 256f
S
for Long Frame operation, and 128f
S
for Short
Frame operation. The length and rate of the TDM frame is
auto−detected by the audio serial port. Long Frame
operation is supported for Single and Dual rate sampling
modes only. Short Frame operation is supported for all
sampling modes.
For the TDM data formats, the maximum BCK rate is
27.648MHz for either Long or Short Frame operation. The
LRCK clock operates at f
S
, the output sampling rate. The
minimum clock high time for the LRCK clock is one BCK
clock period. The start of frame is referenced to the rising
edge of the LRCK signal.
Sub-frame selection for Long Frame TDM operation is
accomplished by using the SUB input (pin 39). When SUB
= 0, the PCM4204 is assigned to sub-frame 0. The
SDOUT1 pin will be driven during sub-frame 0 and
tri-stated during sub-frame 1. When SUB = 1, the
PCM4204 is assigned to sub-frame 1. The SDOUT1 pin
will be driven during sub-frame 1 and tri-stated during
sub-frame 0. For Short Frame TDM operation, the SUB pin
is ignored, although driving or hardwiring the SUB pin low
is an acceptable practice. Figure 7 shows two PCM4204
devices and an audio DSP in a typical TDM format
application.
Figure 8 and Figure 9 illustrate the PCM4204 audio serial
port timing for both Master and Slave mode operation.
System Clock
SUB
SUB
PCM4204
PCM4204
Device #1
(Sub−Frame 0)
Device #2
(Sub−Frame 1)
SCKI
V
CC
FSR
CLKR
DR
LRCK
BCK
SDOUT1
LRCK
BCK
SDOUT1
DSP
Figure 7. TDM Connections for Two PCM4204 Devices and an Audio DSP