Datasheet

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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
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19
LRCK
No BCK Delay
LRCK
One BCK Delay
SDOUT1
Supports 8 Channels, or
two PCM4204 devices.
Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8
Ch.1 Ch.2 Ch.3 Ch.4 Ch.1 Ch.2 Ch.3 Ch.4
Sub−Frame 0
(SUB = 0)
Sub−Frame 1
(SUB = 1)
One Frame
BCK = 256f
S
InthecaseofBCK=256f
S
, each time slot is 32 bits long and contains the 24−bit audio data for the corresponding channel.
The audio data is left justified in the time slot, with the the least significant 8 bits of each time slot being don’tcarebits.
Audio data is always presented in two’s complement, MSB−first format.
TDM Data Format
−
Long Frame (Single and Dual Rate Sampling Modes)
TDM Data Format
−
Short Frame (All Sampling Modes)
LRCK
No BCK Delay
LRCK
One BCK Delay
SDOUT1
Supports 4 Channels, or
two PCM4204 devices.
Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8
Ch.1 Ch.2 Ch.3 Ch.4 Ch.1 Ch.2 Ch.3 Ch.4
One Frame
BCK = 128f
S
(the SUB pin is ignored when using a Short Frame)
−
Figure 4. PCM Data Formats: Time Division Multiplexed (TDM)
DSDCLK
DSD1
DSD2
DSD3
DSD4
D
N−3
D
N−2
D
N−1
D
N
D
N+1
D
N+2
D
N+3
D
N+4
Figure 5. DSD Input and Output Data Format
AUDIO SERIAL PORT OPERATION
This section provides additional details regarding the
PCM4204 audio serial port, utilized for 24-bit linear PCM
output data. The serial port is comprised of four signals:
BCK (pin 29), LRCK (pin 30), SDOUT1 (pin 31), and
SDOUT2 (pin 32). The BCK signal functions as the data (or
bit) clock for the serial audio data. The LRCK is the
left/right word or TDM frame synchronization clock for the
audio serial port. The LRCK and BCK clocks must be
synchronous. The SDOUT1 and SDOUT2 signals are the
serial audio data outputs, with data being clocked out on
the falling edge of the BCK clock. SDOUT1 carries data for
Channels 1 and 2 when using Left-Justified, Right-
Justified, or I
2
S data formats. SDOUT1 carries data for all
four channels when using TDM data formats. SDOUT2
carries data for Channels 3 and 4 when using Left-
Justified, Right-Justified, or I
2
S data formats. SDOUT2 is
forced low when using TDM data formats.
As mentioned in the Audio Data Format section of this
datasheet, the audio serial port can operate in Master or
Slave mode. In Master mode, the BCK and LRCK clock
signals are outputs, derived from the system clock input,
SCKI. The BCK clock is fixed at 128f
S
for Single Rate
sampling mode, and at 64f
S
for Dual or Quad Rate
sampling modes. The LRCK clock operates at f
S
, the
output sampling rate (that is, 48kHz, 96kHz, etc.).